source: rtems/cpukit/score/cpu/sparc/cpu.c @ 59d5575

Last change on this file since 59d5575 was 59d5575, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 5, 2005 at 7:30:18 PM

2005-10-05 Jiri Gaisler <jiri@…>

Edvin Catovic <edvin@…>
Konrad Eisele <konrad@…>

PR 827/bsps

  • ChangeLog?, cpu.c, cpu_asm.S, rtems/score/cpu.h: Portion of large update of SPARC BSPs. Includes addition of sis, leon2 and leon3 BSPs, deletion of leon BSP, addition of SMC91111 NIC driver and much more.
  • Property mode set to 100644
File size: 8.9 KB
Line 
1/*
2 *  SPARC Dependent Source
3 *
4 *  COPYRIGHT (c) 1989-1999.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16#include <rtems/rtems/cache.h>
17
18/*
19 *  This initializes the set of opcodes placed in each trap
20 *  table entry.  The routine which installs a handler is responsible
21 *  for filling in the fields for the _handler address and the _vector
22 *  trap type.
23 *
24 *  The constants following this structure are masks for the fields which
25 *  must be filled in when the handler is installed.
26 */
27
28const CPU_Trap_table_entry _CPU_Trap_slot_template = {
29  0xa1480000,      /* mov   %psr, %l0           */
30  0x29000000,      /* sethi %hi(_handler), %l4  */
31  0x81c52000,      /* jmp   %l4 + %lo(_handler) */
32  0xa6102000       /* mov   _vector, %l3        */
33};
34
35/*PAGE
36 *
37 *  _CPU_Initialize
38 *
39 *  This routine performs processor dependent initialization.
40 *
41 *  Input Parameters:
42 *    cpu_table       - CPU table to initialize
43 *    thread_dispatch - address of disptaching routine
44 *
45 *  Output Parameters: NONE
46 *
47 *  NOTE: There is no need to save the pointer to the thread dispatch routine.
48 *        The SPARC's assembly code can reference it directly with no problems.
49 */
50
51void _CPU_Initialize(
52  rtems_cpu_table  *cpu_table,
53  void            (*thread_dispatch)      /* ignored on this CPU */
54)
55{
56  void                  *pointer;
57
58  /*
59   *  FP context is initialized.  The NULL fp context is copied it to
60   *  the task's FP context during Context_Initialize.
61   */
62
63  pointer = &_CPU_Null_fp_context;
64  _CPU_Context_initialize_fp(pointer);
65
66  /*
67   *  Grab our own copy of the user's CPU table.
68   */
69
70  _CPU_Table = *cpu_table;
71}
72
73/*PAGE
74 *
75 *  _CPU_ISR_Get_level
76 *
77 *  Input Parameters: NONE
78 *
79 *  Output Parameters:
80 *    returns the current interrupt level (PIL field of the PSR)
81 */
82 
83unsigned32 _CPU_ISR_Get_level( void )
84{
85  unsigned32 level;
86 
87  sparc_get_interrupt_level( level );
88 
89  return level;
90}
91
92/*PAGE
93 *
94 *  _CPU_ISR_install_raw_handler
95 *
96 *  This routine installs the specified handler as a "raw" non-executive
97 *  supported trap handler (a.k.a. interrupt service routine).
98 *
99 *  Input Parameters:
100 *    vector      - trap table entry number plus synchronous
101 *                    vs. asynchronous information
102 *    new_handler - address of the handler to be installed
103 *    old_handler - pointer to an address of the handler previously installed
104 *
105 *  Output Parameters: NONE
106 *    *new_handler - address of the handler previously installed
107 *
108 *  NOTE:
109 *
110 *  On the SPARC, there are really only 256 vectors.  However, the executive
111 *  has no easy, fast, reliable way to determine which traps are synchronous
112 *  and which are asynchronous.  By default, synchronous traps return to the
113 *  instruction which caused the interrupt.  So if you install a software
114 *  trap handler as an executive interrupt handler (which is desirable since
115 *  RTEMS takes care of window and register issues), then the executive needs
116 *  to know that the return address is to the trap rather than the instruction
117 *  following the trap.
118 *
119 *  So vectors 0 through 255 are treated as regular asynchronous traps which
120 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
121 *  by the executive to be synchronous and to require that the return address
122 *  be fudged.
123 *
124 *  If you use this mechanism to install a trap handler which must reexecute
125 *  the instruction which caused the trap, then it should be installed as
126 *  an asynchronous trap.  This will avoid the executive changing the return
127 *  address.
128 */
129 
130void _CPU_ISR_install_raw_handler(
131  unsigned32  vector,
132  proc_ptr    new_handler,
133  proc_ptr   *old_handler
134)
135{
136  unsigned32             real_vector;
137  CPU_Trap_table_entry  *tbr;
138  CPU_Trap_table_entry  *slot;
139  unsigned32             u32_tbr;
140  unsigned32             u32_handler;
141
142  /*
143   *  Get the "real" trap number for this vector ignoring the synchronous
144   *  versus asynchronous indicator included with our vector numbers.
145   */
146
147  real_vector = SPARC_REAL_TRAP_NUMBER( vector );
148
149  /*
150   *  Get the current base address of the trap table and calculate a pointer
151   *  to the slot we are interested in.
152   */
153
154  sparc_get_tbr( u32_tbr );
155
156  u32_tbr &= 0xfffff000;
157
158  tbr = (CPU_Trap_table_entry *) u32_tbr;
159
160  slot = &tbr[ real_vector ];
161
162  /*
163   *  Get the address of the old_handler from the trap table.
164   *
165   *  NOTE: The old_handler returned will be bogus if it does not follow
166   *        the RTEMS model.
167   */
168
169#define HIGH_BITS_MASK   0xFFFFFC00
170#define HIGH_BITS_SHIFT  10
171#define LOW_BITS_MASK    0x000003FF
172
173  if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
174    u32_handler = 
175      ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) |
176      (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
177    *old_handler = (proc_ptr) u32_handler;
178  } else
179    *old_handler = 0;
180
181  /*
182   *  Copy the template to the slot and then fix it.
183   */
184
185  *slot = _CPU_Trap_slot_template;
186
187  u32_handler = (unsigned32) new_handler;
188
189  slot->mov_vector_l3 |= vector;
190  slot->sethi_of_handler_to_l4 |= 
191    (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
192  slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
193
194  /* need to flush icache after this !!! */
195
196  rtems_cache_invalidate_entire_instruction();
197
198}
199
200/*PAGE
201 *
202 *  _CPU_ISR_install_vector
203 *
204 *  This kernel routine installs the RTEMS handler for the
205 *  specified vector.
206 *
207 *  Input parameters:
208 *    vector       - interrupt vector number
209 *    new_handler  - replacement ISR for this vector number
210 *    old_handler  - pointer to former ISR for this vector number
211 *
212 *  Output parameters:
213 *    *old_handler - former ISR for this vector number
214 *
215 */
216
217void _CPU_ISR_install_vector(
218  unsigned32  vector,
219  proc_ptr    new_handler,
220  proc_ptr   *old_handler
221)
222{
223   unsigned32 real_vector;
224   proc_ptr   ignored;
225
226  /*
227   *  Get the "real" trap number for this vector ignoring the synchronous
228   *  versus asynchronous indicator included with our vector numbers.
229   */
230
231   real_vector = SPARC_REAL_TRAP_NUMBER( vector );
232
233   /*
234    *  Return the previous ISR handler.
235    */
236
237   *old_handler = _ISR_Vector_table[ real_vector ];
238
239   /*
240    *  Install the wrapper so this ISR can be invoked properly.
241    */
242
243   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
244
245   /*
246    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
247    *  be used by the _ISR_Handler so the user gets control.
248    */
249
250    _ISR_Vector_table[ real_vector ] = new_handler;
251}
252
253/*PAGE
254 *
255 *  _CPU_Context_Initialize
256 *
257 *  This kernel routine initializes the basic non-FP context area associated
258 *  with each thread.
259 *
260 *  Input parameters:
261 *    the_context  - pointer to the context area
262 *    stack_base   - address of memory for the SPARC
263 *    size         - size in bytes of the stack area
264 *    new_level    - interrupt level for this context area
265 *    entry_point  - the starting execution point for this this context
266 *    is_fp        - TRUE if this context is associated with an FP thread
267 *
268 *  Output parameters: NONE
269 */
270
271void _CPU_Context_Initialize(
272  Context_Control  *the_context,
273  unsigned32       *stack_base,
274  unsigned32        size,
275  unsigned32        new_level,
276  void             *entry_point,
277  boolean           is_fp
278)
279{
280    unsigned32   stack_high;  /* highest "stack aligned" address */
281    unsigned32   the_size;
282    unsigned32   tmp_psr;
283 
284    /*
285     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
286     *  based on the stack_high address. 
287     */
288 
289    stack_high = ((unsigned32)(stack_base) + size);
290    stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
291 
292    the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
293 
294    /*
295     *  See the README in this directory for a diagram of the stack.
296     */
297 
298    the_context->o7    = ((unsigned32) entry_point) - 8;
299    the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
300    the_context->i6_fp = stack_high;
301
302    /*
303     *  Build the PSR for the task.  Most everything can be 0 and the
304     *  CWP is corrected during the context switch.
305     *
306     *  The EF bit determines if the floating point unit is available.
307     *  The FPU is ONLY enabled if the context is associated with an FP task
308     *  and this SPARC model has an FPU.
309     */
310
311    sparc_get_psr( tmp_psr );
312    tmp_psr &= ~SPARC_PSR_PIL_MASK;
313    tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
314    tmp_psr &= ~SPARC_PSR_EF_MASK;      /* disabled by default */
315   
316    /*
317     *  If this bit is not set, then a task gets a fault when it accesses
318     *  a floating point register.  This is a nice way to detect floating
319     *  point tasks which are not currently declared as such.
320     */
321
322    if ( is_fp )
323      tmp_psr |= SPARC_PSR_EF_MASK;
324
325    the_context->psr = tmp_psr;
326}
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