source: rtems/cpukit/score/cpu/sparc/cpu.c @ 5996c48

4.104.114.84.95
Last change on this file since 5996c48 was 5996c48, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 6, 2000 at 3:33:12 PM

2000-12-06 Joel Sherrill <joel@…>

  • cpu.c: Added include of <rtems/rtems/cache.h> to eliminate warning.
  • Property mode set to 100644
File size: 10.0 KB
Line 
1/*
2 *  SPARC Dependent Source
3 *
4 *  COPYRIGHT (c) 1989-1999.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 *  $Id$
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16#include <rtems/rtems/cache.h>
17
18/*
19 *  This initializes the set of opcodes placed in each trap
20 *  table entry.  The routine which installs a handler is responsible
21 *  for filling in the fields for the _handler address and the _vector
22 *  trap type.
23 *
24 *  The constants following this structure are masks for the fields which
25 *  must be filled in when the handler is installed.
26 */
27
28const CPU_Trap_table_entry _CPU_Trap_slot_template = {
29  0xa1480000,      /* mov   %psr, %l0           */
30  0x29000000,      /* sethi %hi(_handler), %l4  */
31  0x81c52000,      /* jmp   %l4 + %lo(_handler) */
32  0xa6102000       /* mov   _vector, %l3        */
33};
34
35/*PAGE
36 *
37 *  _CPU_Initialize
38 *
39 *  This routine performs processor dependent initialization.
40 *
41 *  Input Parameters:
42 *    cpu_table       - CPU table to initialize
43 *    thread_dispatch - address of disptaching routine
44 *
45 *  Output Parameters: NONE
46 *
47 *  NOTE: There is no need to save the pointer to the thread dispatch routine.
48 *        The SPARC's assembly code can reference it directly with no problems.
49 */
50
51void _CPU_Initialize(
52  rtems_cpu_table  *cpu_table,
53  void            (*thread_dispatch)      /* ignored on this CPU */
54)
55{
56  void                  *pointer;
57
58#ifndef NO_TABLE_MOVE
59  unsigned32             trap_table_start;
60  unsigned32             tbr_value;
61  CPU_Trap_table_entry  *old_tbr;
62  CPU_Trap_table_entry  *trap_table;
63
64  /*
65   *  Install the executive's trap table.  All entries from the original
66   *  trap table are copied into the executive's trap table.  This is essential
67   *  since this preserves critical trap handlers such as the window underflow
68   *  and overflow handlers.  It is the responsibility of the BSP to provide
69   *  install these in the initial trap table.
70   */
71
72 
73  trap_table_start = (unsigned32) &_CPU_Trap_Table_area;
74  if (trap_table_start & (SPARC_TRAP_TABLE_ALIGNMENT-1))
75    trap_table_start = (trap_table_start + SPARC_TRAP_TABLE_ALIGNMENT) & 
76                       ~(SPARC_TRAP_TABLE_ALIGNMENT-1);
77
78  trap_table = (CPU_Trap_table_entry *) trap_table_start;
79
80  sparc_get_tbr( tbr_value );
81
82  old_tbr = (CPU_Trap_table_entry *) (tbr_value & 0xfffff000);
83
84  memcpy( trap_table, (void *) old_tbr, 256 * sizeof( CPU_Trap_table_entry ) );
85
86  sparc_set_tbr( trap_table_start );
87
88#endif
89
90#if (SPARC_HAS_FPU == 1)
91
92  /*
93   *  This seems to be the most appropriate way to obtain an initial
94   *  FP context on the SPARC.  The NULL fp context is copied it to
95   *  the task's FP context during Context_Initialize.
96   */
97
98  pointer = &_CPU_Null_fp_context;
99  _CPU_Context_save_fp( &pointer );
100#endif
101
102  /*
103   *  Grab our own copy of the user's CPU table.
104   */
105
106  _CPU_Table = *cpu_table;
107}
108
109/*PAGE
110 *
111 *  _CPU_ISR_Get_level
112 *
113 *  Input Parameters: NONE
114 *
115 *  Output Parameters:
116 *    returns the current interrupt level (PIL field of the PSR)
117 */
118 
119unsigned32 _CPU_ISR_Get_level( void )
120{
121  unsigned32 level;
122 
123  sparc_get_interrupt_level( level );
124 
125  return level;
126}
127
128/*PAGE
129 *
130 *  _CPU_ISR_install_raw_handler
131 *
132 *  This routine installs the specified handler as a "raw" non-executive
133 *  supported trap handler (a.k.a. interrupt service routine).
134 *
135 *  Input Parameters:
136 *    vector      - trap table entry number plus synchronous
137 *                    vs. asynchronous information
138 *    new_handler - address of the handler to be installed
139 *    old_handler - pointer to an address of the handler previously installed
140 *
141 *  Output Parameters: NONE
142 *    *new_handler - address of the handler previously installed
143 *
144 *  NOTE:
145 *
146 *  On the SPARC, there are really only 256 vectors.  However, the executive
147 *  has no easy, fast, reliable way to determine which traps are synchronous
148 *  and which are asynchronous.  By default, synchronous traps return to the
149 *  instruction which caused the interrupt.  So if you install a software
150 *  trap handler as an executive interrupt handler (which is desirable since
151 *  RTEMS takes care of window and register issues), then the executive needs
152 *  to know that the return address is to the trap rather than the instruction
153 *  following the trap.
154 *
155 *  So vectors 0 through 255 are treated as regular asynchronous traps which
156 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
157 *  by the executive to be synchronous and to require that the return address
158 *  be fudged.
159 *
160 *  If you use this mechanism to install a trap handler which must reexecute
161 *  the instruction which caused the trap, then it should be installed as
162 *  an asynchronous trap.  This will avoid the executive changing the return
163 *  address.
164 */
165 
166void _CPU_ISR_install_raw_handler(
167  unsigned32  vector,
168  proc_ptr    new_handler,
169  proc_ptr   *old_handler
170)
171{
172  unsigned32             real_vector;
173  CPU_Trap_table_entry  *tbr;
174  CPU_Trap_table_entry  *slot;
175  unsigned32             u32_tbr;
176  unsigned32             u32_handler;
177
178  /*
179   *  Get the "real" trap number for this vector ignoring the synchronous
180   *  versus asynchronous indicator included with our vector numbers.
181   */
182
183  real_vector = SPARC_REAL_TRAP_NUMBER( vector );
184
185  /*
186   *  Get the current base address of the trap table and calculate a pointer
187   *  to the slot we are interested in.
188   */
189
190  sparc_get_tbr( u32_tbr );
191
192  u32_tbr &= 0xfffff000;
193
194  tbr = (CPU_Trap_table_entry *) u32_tbr;
195
196  slot = &tbr[ real_vector ];
197
198  /*
199   *  Get the address of the old_handler from the trap table.
200   *
201   *  NOTE: The old_handler returned will be bogus if it does not follow
202   *        the RTEMS model.
203   */
204
205#define HIGH_BITS_MASK   0xFFFFFC00
206#define HIGH_BITS_SHIFT  10
207#define LOW_BITS_MASK    0x000003FF
208
209  if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
210    u32_handler = 
211      ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) |
212      (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
213    *old_handler = (proc_ptr) u32_handler;
214  } else
215    *old_handler = 0;
216
217  /*
218   *  Copy the template to the slot and then fix it.
219   */
220
221  *slot = _CPU_Trap_slot_template;
222
223  u32_handler = (unsigned32) new_handler;
224
225  slot->mov_vector_l3 |= vector;
226  slot->sethi_of_handler_to_l4 |= 
227    (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
228  slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
229
230  /* need to flush icache after this !!! */
231
232  rtems_cache_invalidate_entire_instruction();
233
234}
235
236/*PAGE
237 *
238 *  _CPU_ISR_install_vector
239 *
240 *  This kernel routine installs the RTEMS handler for the
241 *  specified vector.
242 *
243 *  Input parameters:
244 *    vector       - interrupt vector number
245 *    new_handler  - replacement ISR for this vector number
246 *    old_handler  - pointer to former ISR for this vector number
247 *
248 *  Output parameters:
249 *    *old_handler - former ISR for this vector number
250 *
251 */
252
253void _CPU_ISR_install_vector(
254  unsigned32  vector,
255  proc_ptr    new_handler,
256  proc_ptr   *old_handler
257)
258{
259   unsigned32 real_vector;
260   proc_ptr   ignored;
261
262  /*
263   *  Get the "real" trap number for this vector ignoring the synchronous
264   *  versus asynchronous indicator included with our vector numbers.
265   */
266
267   real_vector = SPARC_REAL_TRAP_NUMBER( vector );
268
269   /*
270    *  Return the previous ISR handler.
271    */
272
273   *old_handler = _ISR_Vector_table[ real_vector ];
274
275   /*
276    *  Install the wrapper so this ISR can be invoked properly.
277    */
278
279   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
280
281   /*
282    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
283    *  be used by the _ISR_Handler so the user gets control.
284    */
285
286    _ISR_Vector_table[ real_vector ] = new_handler;
287}
288
289/*PAGE
290 *
291 *  _CPU_Context_Initialize
292 *
293 *  This kernel routine initializes the basic non-FP context area associated
294 *  with each thread.
295 *
296 *  Input parameters:
297 *    the_context  - pointer to the context area
298 *    stack_base   - address of memory for the SPARC
299 *    size         - size in bytes of the stack area
300 *    new_level    - interrupt level for this context area
301 *    entry_point  - the starting execution point for this this context
302 *    is_fp        - TRUE if this context is associated with an FP thread
303 *
304 *  Output parameters: NONE
305 */
306
307void _CPU_Context_Initialize(
308  Context_Control  *the_context,
309  unsigned32       *stack_base,
310  unsigned32        size,
311  unsigned32        new_level,
312  void             *entry_point,
313  boolean           is_fp
314)
315{
316    unsigned32   stack_high;  /* highest "stack aligned" address */
317    unsigned32   the_size;
318    unsigned32   tmp_psr;
319 
320    /*
321     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
322     *  based on the stack_high address. 
323     */
324 
325    stack_high = ((unsigned32)(stack_base) + size);
326    stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
327 
328    the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
329 
330    /*
331     *  See the README in this directory for a diagram of the stack.
332     */
333 
334    the_context->o7    = ((unsigned32) entry_point) - 8;
335    the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
336    the_context->i6_fp = stack_high;
337
338    /*
339     *  Build the PSR for the task.  Most everything can be 0 and the
340     *  CWP is corrected during the context switch.
341     *
342     *  The EF bit determines if the floating point unit is available.
343     *  The FPU is ONLY enabled if the context is associated with an FP task
344     *  and this SPARC model has an FPU.
345     */
346
347    sparc_get_psr( tmp_psr );
348    tmp_psr &= ~SPARC_PSR_PIL_MASK;
349    tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
350    tmp_psr &= ~SPARC_PSR_EF_MASK;      /* disabled by default */
351   
352#if (SPARC_HAS_FPU == 1)
353    /*
354     *  If this bit is not set, then a task gets a fault when it accesses
355     *  a floating point register.  This is a nice way to detect floating
356     *  point tasks which are not currently declared as such.
357     */
358
359    if ( is_fp )
360      tmp_psr |= SPARC_PSR_EF_MASK;
361#endif
362    the_context->psr = tmp_psr;
363}
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