1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief SPARC CPU Dependent Source |
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5 | */ |
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6 | |
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7 | /* |
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8 | * COPYRIGHT (c) 1989-2007. |
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9 | * On-Line Applications Research Corporation (OAR). |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.org/license/LICENSE. |
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14 | */ |
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15 | |
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16 | #ifdef HAVE_CONFIG_H |
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17 | #include "config.h" |
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18 | #endif |
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19 | |
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20 | #include <rtems/system.h> |
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21 | #include <rtems/score/isr.h> |
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22 | #include <rtems/score/percpu.h> |
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23 | #include <rtems/score/tls.h> |
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24 | #include <rtems/rtems/cache.h> |
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25 | |
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26 | #if SPARC_HAS_FPU == 1 |
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27 | RTEMS_STATIC_ASSERT( |
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28 | offsetof( Per_CPU_Control, cpu_per_cpu.fsr) |
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29 | == SPARC_PER_CPU_FSR_OFFSET, |
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30 | SPARC_PER_CPU_FSR_OFFSET |
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31 | ); |
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32 | #endif |
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33 | |
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34 | #define SPARC_ASSERT_OFFSET(field, off) \ |
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35 | RTEMS_STATIC_ASSERT( \ |
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36 | offsetof(Context_Control, field) == off ## _OFFSET, \ |
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37 | Context_Control_offset_ ## field \ |
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38 | ) |
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39 | |
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40 | SPARC_ASSERT_OFFSET(g5, G5); |
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41 | SPARC_ASSERT_OFFSET(g7, G7); |
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42 | |
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43 | RTEMS_STATIC_ASSERT( |
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44 | offsetof(Context_Control, l0_and_l1) == L0_OFFSET, |
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45 | Context_Control_offset_L0 |
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46 | ); |
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47 | |
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48 | RTEMS_STATIC_ASSERT( |
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49 | offsetof(Context_Control, l0_and_l1) + 4 == L1_OFFSET, |
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50 | Context_Control_offset_L1 |
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51 | ); |
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52 | |
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53 | SPARC_ASSERT_OFFSET(l2, L2); |
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54 | SPARC_ASSERT_OFFSET(l3, L3); |
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55 | SPARC_ASSERT_OFFSET(l4, L4); |
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56 | SPARC_ASSERT_OFFSET(l5, L5); |
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57 | SPARC_ASSERT_OFFSET(l6, L6); |
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58 | SPARC_ASSERT_OFFSET(l7, L7); |
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59 | SPARC_ASSERT_OFFSET(i0, I0); |
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60 | SPARC_ASSERT_OFFSET(i1, I1); |
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61 | SPARC_ASSERT_OFFSET(i2, I2); |
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62 | SPARC_ASSERT_OFFSET(i3, I3); |
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63 | SPARC_ASSERT_OFFSET(i4, I4); |
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64 | SPARC_ASSERT_OFFSET(i5, I5); |
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65 | SPARC_ASSERT_OFFSET(i6_fp, I6_FP); |
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66 | SPARC_ASSERT_OFFSET(i7, I7); |
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67 | SPARC_ASSERT_OFFSET(o6_sp, O6_SP); |
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68 | SPARC_ASSERT_OFFSET(o7, O7); |
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69 | SPARC_ASSERT_OFFSET(psr, PSR); |
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70 | SPARC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE_STACK); |
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71 | |
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72 | #if defined(RTEMS_SMP) |
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73 | SPARC_ASSERT_OFFSET(is_executing, SPARC_CONTEXT_CONTROL_IS_EXECUTING); |
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74 | #endif |
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75 | |
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76 | #define SPARC_ASSERT_ISF_OFFSET(field, off) \ |
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77 | RTEMS_STATIC_ASSERT( \ |
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78 | offsetof(CPU_Interrupt_frame, field) == ISF_ ## off ## _OFFSET, \ |
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79 | CPU_Interrupt_frame_offset_ ## field \ |
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80 | ) |
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81 | |
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82 | SPARC_ASSERT_ISF_OFFSET(psr, PSR); |
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83 | SPARC_ASSERT_ISF_OFFSET(pc, PC); |
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84 | SPARC_ASSERT_ISF_OFFSET(npc, NPC); |
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85 | SPARC_ASSERT_ISF_OFFSET(g1, G1); |
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86 | SPARC_ASSERT_ISF_OFFSET(g2, G2); |
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87 | SPARC_ASSERT_ISF_OFFSET(g3, G3); |
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88 | SPARC_ASSERT_ISF_OFFSET(g4, G4); |
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89 | SPARC_ASSERT_ISF_OFFSET(g5, G5); |
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90 | SPARC_ASSERT_ISF_OFFSET(g7, G7); |
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91 | SPARC_ASSERT_ISF_OFFSET(i0, I0); |
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92 | SPARC_ASSERT_ISF_OFFSET(i1, I1); |
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93 | SPARC_ASSERT_ISF_OFFSET(i2, I2); |
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94 | SPARC_ASSERT_ISF_OFFSET(i3, I3); |
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95 | SPARC_ASSERT_ISF_OFFSET(i4, I4); |
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96 | SPARC_ASSERT_ISF_OFFSET(i5, I5); |
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97 | SPARC_ASSERT_ISF_OFFSET(i6_fp, I6_FP); |
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98 | SPARC_ASSERT_ISF_OFFSET(i7, I7); |
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99 | SPARC_ASSERT_ISF_OFFSET(y, Y); |
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100 | SPARC_ASSERT_ISF_OFFSET(tpc, TPC); |
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101 | |
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102 | RTEMS_STATIC_ASSERT( |
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103 | sizeof(SPARC_Minimum_stack_frame) == SPARC_MINIMUM_STACK_FRAME_SIZE, |
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104 | SPARC_MINIMUM_STACK_FRAME_SIZE |
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105 | ); |
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106 | |
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107 | /* https://devel.rtems.org/ticket/2352 */ |
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108 | RTEMS_STATIC_ASSERT( |
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109 | sizeof(CPU_Interrupt_frame) % CPU_ALIGNMENT == 0, |
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110 | CPU_Interrupt_frame_alignment |
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111 | ); |
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112 | |
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113 | #if (SPARC_HAS_FPU == 1) && !defined(SPARC_USE_SAFE_FP_SUPPORT) |
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114 | Context_Control_fp _CPU_Null_fp_context; |
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115 | #endif |
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116 | |
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117 | /* |
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118 | * _CPU_Initialize |
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119 | * |
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120 | * This routine performs processor dependent initialization. |
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121 | * |
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122 | * INPUT PARAMETERS: NONE |
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123 | * |
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124 | * Output Parameters: NONE |
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125 | * |
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126 | * NOTE: There is no need to save the pointer to the thread dispatch routine. |
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127 | * The SPARC's assembly code can reference it directly with no problems. |
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128 | */ |
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129 | |
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130 | void _CPU_Initialize(void) |
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131 | { |
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132 | #if (SPARC_HAS_FPU == 1) && !defined(SPARC_USE_SAFE_FP_SUPPORT) |
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133 | Context_Control_fp *pointer; |
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134 | uint32_t psr; |
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135 | |
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136 | sparc_get_psr( psr ); |
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137 | psr |= SPARC_PSR_EF_MASK; |
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138 | sparc_set_psr( psr ); |
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139 | |
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140 | /* |
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141 | * This seems to be the most appropriate way to obtain an initial |
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142 | * FP context on the SPARC. The NULL fp context is copied it to |
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143 | * the task's FP context during Context_Initialize. |
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144 | */ |
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145 | |
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146 | pointer = &_CPU_Null_fp_context; |
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147 | _CPU_Context_save_fp( &pointer ); |
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148 | #endif |
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149 | } |
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150 | |
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151 | uint32_t _CPU_ISR_Get_level( void ) |
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152 | { |
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153 | uint32_t level; |
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154 | |
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155 | sparc_get_interrupt_level( level ); |
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156 | |
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157 | return level; |
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158 | } |
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159 | |
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160 | /* |
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161 | * _CPU_ISR_install_raw_handler |
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162 | * |
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163 | * This routine installs the specified handler as a "raw" non-executive |
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164 | * supported trap handler (a.k.a. interrupt service routine). |
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165 | * |
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166 | * Input Parameters: |
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167 | * vector - trap table entry number plus synchronous |
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168 | * vs. asynchronous information |
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169 | * new_handler - address of the handler to be installed |
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170 | * old_handler - pointer to an address of the handler previously installed |
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171 | * |
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172 | * Output Parameters: NONE |
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173 | * *new_handler - address of the handler previously installed |
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174 | * |
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175 | * NOTE: |
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176 | * |
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177 | * On the SPARC, there are really only 256 vectors. However, the executive |
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178 | * has no easy, fast, reliable way to determine which traps are synchronous |
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179 | * and which are asynchronous. By default, synchronous traps return to the |
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180 | * instruction which caused the interrupt. So if you install a software |
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181 | * trap handler as an executive interrupt handler (which is desirable since |
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182 | * RTEMS takes care of window and register issues), then the executive needs |
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183 | * to know that the return address is to the trap rather than the instruction |
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184 | * following the trap. |
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185 | * |
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186 | * So vectors 0 through 255 are treated as regular asynchronous traps which |
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187 | * provide the "correct" return address. Vectors 256 through 512 are assumed |
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188 | * by the executive to be synchronous and to require that the return address |
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189 | * be fudged. |
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190 | * |
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191 | * If you use this mechanism to install a trap handler which must reexecute |
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192 | * the instruction which caused the trap, then it should be installed as |
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193 | * an asynchronous trap. This will avoid the executive changing the return |
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194 | * address. |
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195 | */ |
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196 | |
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197 | void _CPU_ISR_install_raw_handler( |
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198 | uint32_t vector, |
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199 | proc_ptr new_handler, |
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200 | proc_ptr *old_handler |
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201 | ) |
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202 | { |
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203 | uint32_t real_vector; |
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204 | CPU_Trap_table_entry *tbr; |
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205 | CPU_Trap_table_entry *slot; |
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206 | uint32_t u32_tbr; |
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207 | uint32_t u32_handler; |
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208 | |
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209 | /* |
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210 | * Get the "real" trap number for this vector ignoring the synchronous |
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211 | * versus asynchronous indicator included with our vector numbers. |
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212 | */ |
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213 | |
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214 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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215 | |
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216 | /* |
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217 | * Get the current base address of the trap table and calculate a pointer |
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218 | * to the slot we are interested in. |
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219 | */ |
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220 | |
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221 | sparc_get_tbr( u32_tbr ); |
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222 | |
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223 | u32_tbr &= 0xfffff000; |
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224 | |
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225 | tbr = (CPU_Trap_table_entry *) u32_tbr; |
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226 | |
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227 | slot = &tbr[ real_vector ]; |
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228 | |
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229 | /* |
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230 | * Get the address of the old_handler from the trap table. |
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231 | * |
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232 | * NOTE: The old_handler returned will be bogus if it does not follow |
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233 | * the RTEMS model. |
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234 | */ |
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235 | |
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236 | #define HIGH_BITS_MASK 0xFFFFFC00 |
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237 | #define HIGH_BITS_SHIFT 10 |
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238 | #define LOW_BITS_MASK 0x000003FF |
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239 | |
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240 | if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) { |
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241 | u32_handler = |
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242 | (slot->sethi_of_handler_to_l4 << HIGH_BITS_SHIFT) | |
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243 | (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK); |
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244 | *old_handler = (proc_ptr) u32_handler; |
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245 | } else |
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246 | *old_handler = 0; |
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247 | |
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248 | /* |
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249 | * Copy the template to the slot and then fix it. |
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250 | */ |
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251 | |
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252 | *slot = _CPU_Trap_slot_template; |
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253 | |
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254 | u32_handler = (uint32_t) new_handler; |
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255 | |
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256 | slot->mov_vector_l3 |= vector; |
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257 | slot->sethi_of_handler_to_l4 |= |
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258 | (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT; |
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259 | slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK); |
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260 | |
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261 | /* |
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262 | * There is no instruction cache snooping, so we need to invalidate |
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263 | * the instruction cache to make sure that the processor sees the |
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264 | * changes to the trap table. This step is required on both single- |
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265 | * and multiprocessor systems. |
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266 | * |
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267 | * In a SMP configuration a change to the trap table might be |
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268 | * missed by other cores. If the system state is up, the other |
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269 | * cores can be notified using SMP messages that they need to |
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270 | * flush their icache. If the up state has not been reached |
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271 | * there is no need to notify other cores. They will do an |
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272 | * automatic flush of the icache just after entering the up |
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273 | * state, but before enabling interrupts. |
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274 | */ |
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275 | rtems_cache_invalidate_entire_instruction(); |
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276 | } |
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277 | |
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278 | void _CPU_ISR_install_vector( |
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279 | uint32_t vector, |
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280 | proc_ptr new_handler, |
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281 | proc_ptr *old_handler |
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282 | ) |
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283 | { |
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284 | uint32_t real_vector; |
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285 | proc_ptr ignored; |
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286 | |
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287 | /* |
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288 | * Get the "real" trap number for this vector ignoring the synchronous |
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289 | * versus asynchronous indicator included with our vector numbers. |
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290 | */ |
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291 | |
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292 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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293 | |
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294 | /* |
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295 | * Return the previous ISR handler. |
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296 | */ |
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297 | |
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298 | *old_handler = _ISR_Vector_table[ real_vector ]; |
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299 | |
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300 | /* |
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301 | * Install the wrapper so this ISR can be invoked properly. |
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302 | */ |
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303 | |
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304 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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305 | |
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306 | /* |
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307 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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308 | * be used by the _ISR_Handler so the user gets control. |
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309 | */ |
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310 | |
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311 | _ISR_Vector_table[ real_vector ] = new_handler; |
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312 | } |
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313 | |
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314 | void _CPU_Context_Initialize( |
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315 | Context_Control *the_context, |
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316 | uint32_t *stack_base, |
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317 | uint32_t size, |
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318 | uint32_t new_level, |
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319 | void *entry_point, |
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320 | bool is_fp, |
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321 | void *tls_area |
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322 | ) |
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323 | { |
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324 | uint32_t stack_high; /* highest "stack aligned" address */ |
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325 | uint32_t tmp_psr; |
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326 | |
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327 | /* |
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328 | * On CPUs with stacks which grow down (i.e. SPARC), we build the stack |
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329 | * based on the stack_high address. |
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330 | */ |
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331 | |
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332 | stack_high = ((uint32_t)(stack_base) + size); |
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333 | stack_high &= ~(CPU_STACK_ALIGNMENT - 1); |
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334 | |
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335 | /* |
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336 | * See the README in this directory for a diagram of the stack. |
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337 | */ |
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338 | |
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339 | the_context->o7 = ((uint32_t) entry_point) - 8; |
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340 | the_context->o6_sp = stack_high - SPARC_MINIMUM_STACK_FRAME_SIZE; |
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341 | the_context->i6_fp = 0; |
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342 | |
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343 | /* |
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344 | * Build the PSR for the task. Most everything can be 0 and the |
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345 | * CWP is corrected during the context switch. |
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346 | * |
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347 | * The EF bit determines if the floating point unit is available. |
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348 | * The FPU is ONLY enabled if the context is associated with an FP task |
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349 | * and this SPARC model has an FPU. |
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350 | */ |
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351 | |
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352 | sparc_get_psr( tmp_psr ); |
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353 | tmp_psr &= ~SPARC_PSR_PIL_MASK; |
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354 | tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK; |
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355 | tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */ |
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356 | |
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357 | /* _CPU_Context_restore_heir() relies on this */ |
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358 | _Assert( ( tmp_psr & SPARC_PSR_ET_MASK ) != 0 ); |
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359 | |
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360 | #if (SPARC_HAS_FPU == 1) |
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361 | /* |
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362 | * If this bit is not set, then a task gets a fault when it accesses |
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363 | * a floating point register. This is a nice way to detect floating |
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364 | * point tasks which are not currently declared as such. |
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365 | */ |
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366 | |
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367 | if ( is_fp ) |
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368 | tmp_psr |= SPARC_PSR_EF_MASK; |
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369 | #endif |
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370 | the_context->psr = tmp_psr; |
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371 | |
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372 | /* |
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373 | * Since THIS thread is being created, there is no way that THIS |
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374 | * thread can have an _ISR_Dispatch stack frame on its stack. |
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375 | */ |
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376 | the_context->isr_dispatch_disable = 0; |
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377 | |
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378 | if ( tls_area != NULL ) { |
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379 | void *tcb = _TLS_TCB_after_TLS_block_initialize( tls_area ); |
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380 | |
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381 | the_context->g7 = (uintptr_t) tcb; |
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382 | } |
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383 | } |
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