source: rtems/cpukit/score/cpu/sparc/cpu.c @ 477e2d19

4.104.114.84.95
Last change on this file since 477e2d19 was 477e2d19, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 15, 2000 at 9:33:35 PM

2000-11-14 Jiri Gaisler <jgais@…>

  • cpu.c, rtems/cpu/sparc.h: Make floating point optional based on gcc arguments. Do not initialize FP context if there is no FPU. Flush instruction cache after installing RTEMS trap handler.
  • Property mode set to 100644
File size: 10.0 KB
Line 
1/*
2 *  SPARC Dependent Source
3 *
4 *  COPYRIGHT (c) 1989-1999.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 *  $Id$
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16
17/*
18 *  This initializes the set of opcodes placed in each trap
19 *  table entry.  The routine which installs a handler is responsible
20 *  for filling in the fields for the _handler address and the _vector
21 *  trap type.
22 *
23 *  The constants following this structure are masks for the fields which
24 *  must be filled in when the handler is installed.
25 */
26
27const CPU_Trap_table_entry _CPU_Trap_slot_template = {
28  0xa1480000,      /* mov   %psr, %l0           */
29  0x29000000,      /* sethi %hi(_handler), %l4  */
30  0x81c52000,      /* jmp   %l4 + %lo(_handler) */
31  0xa6102000       /* mov   _vector, %l3        */
32};
33
34/*PAGE
35 *
36 *  _CPU_Initialize
37 *
38 *  This routine performs processor dependent initialization.
39 *
40 *  Input Parameters:
41 *    cpu_table       - CPU table to initialize
42 *    thread_dispatch - address of disptaching routine
43 *
44 *  Output Parameters: NONE
45 *
46 *  NOTE: There is no need to save the pointer to the thread dispatch routine.
47 *        The SPARC's assembly code can reference it directly with no problems.
48 */
49
50void _CPU_Initialize(
51  rtems_cpu_table  *cpu_table,
52  void            (*thread_dispatch)      /* ignored on this CPU */
53)
54{
55  void                  *pointer;
56
57#ifndef NO_TABLE_MOVE
58  unsigned32             trap_table_start;
59  unsigned32             tbr_value;
60  CPU_Trap_table_entry  *old_tbr;
61  CPU_Trap_table_entry  *trap_table;
62
63  /*
64   *  Install the executive's trap table.  All entries from the original
65   *  trap table are copied into the executive's trap table.  This is essential
66   *  since this preserves critical trap handlers such as the window underflow
67   *  and overflow handlers.  It is the responsibility of the BSP to provide
68   *  install these in the initial trap table.
69   */
70
71 
72  trap_table_start = (unsigned32) &_CPU_Trap_Table_area;
73  if (trap_table_start & (SPARC_TRAP_TABLE_ALIGNMENT-1))
74    trap_table_start = (trap_table_start + SPARC_TRAP_TABLE_ALIGNMENT) & 
75                       ~(SPARC_TRAP_TABLE_ALIGNMENT-1);
76
77  trap_table = (CPU_Trap_table_entry *) trap_table_start;
78
79  sparc_get_tbr( tbr_value );
80
81  old_tbr = (CPU_Trap_table_entry *) (tbr_value & 0xfffff000);
82
83  memcpy( trap_table, (void *) old_tbr, 256 * sizeof( CPU_Trap_table_entry ) );
84
85  sparc_set_tbr( trap_table_start );
86
87#endif
88
89#if (SPARC_HAS_FPU == 1)
90
91  /*
92   *  This seems to be the most appropriate way to obtain an initial
93   *  FP context on the SPARC.  The NULL fp context is copied it to
94   *  the task's FP context during Context_Initialize.
95   */
96
97  pointer = &_CPU_Null_fp_context;
98  _CPU_Context_save_fp( &pointer );
99#endif
100
101  /*
102   *  Grab our own copy of the user's CPU table.
103   */
104
105  _CPU_Table = *cpu_table;
106}
107
108/*PAGE
109 *
110 *  _CPU_ISR_Get_level
111 *
112 *  Input Parameters: NONE
113 *
114 *  Output Parameters:
115 *    returns the current interrupt level (PIL field of the PSR)
116 */
117 
118unsigned32 _CPU_ISR_Get_level( void )
119{
120  unsigned32 level;
121 
122  sparc_get_interrupt_level( level );
123 
124  return level;
125}
126
127/*PAGE
128 *
129 *  _CPU_ISR_install_raw_handler
130 *
131 *  This routine installs the specified handler as a "raw" non-executive
132 *  supported trap handler (a.k.a. interrupt service routine).
133 *
134 *  Input Parameters:
135 *    vector      - trap table entry number plus synchronous
136 *                    vs. asynchronous information
137 *    new_handler - address of the handler to be installed
138 *    old_handler - pointer to an address of the handler previously installed
139 *
140 *  Output Parameters: NONE
141 *    *new_handler - address of the handler previously installed
142 *
143 *  NOTE:
144 *
145 *  On the SPARC, there are really only 256 vectors.  However, the executive
146 *  has no easy, fast, reliable way to determine which traps are synchronous
147 *  and which are asynchronous.  By default, synchronous traps return to the
148 *  instruction which caused the interrupt.  So if you install a software
149 *  trap handler as an executive interrupt handler (which is desirable since
150 *  RTEMS takes care of window and register issues), then the executive needs
151 *  to know that the return address is to the trap rather than the instruction
152 *  following the trap.
153 *
154 *  So vectors 0 through 255 are treated as regular asynchronous traps which
155 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
156 *  by the executive to be synchronous and to require that the return address
157 *  be fudged.
158 *
159 *  If you use this mechanism to install a trap handler which must reexecute
160 *  the instruction which caused the trap, then it should be installed as
161 *  an asynchronous trap.  This will avoid the executive changing the return
162 *  address.
163 */
164 
165void _CPU_ISR_install_raw_handler(
166  unsigned32  vector,
167  proc_ptr    new_handler,
168  proc_ptr   *old_handler
169)
170{
171  unsigned32             real_vector;
172  CPU_Trap_table_entry  *tbr;
173  CPU_Trap_table_entry  *slot;
174  unsigned32             u32_tbr;
175  unsigned32             u32_handler;
176
177  /*
178   *  Get the "real" trap number for this vector ignoring the synchronous
179   *  versus asynchronous indicator included with our vector numbers.
180   */
181
182  real_vector = SPARC_REAL_TRAP_NUMBER( vector );
183
184  /*
185   *  Get the current base address of the trap table and calculate a pointer
186   *  to the slot we are interested in.
187   */
188
189  sparc_get_tbr( u32_tbr );
190
191  u32_tbr &= 0xfffff000;
192
193  tbr = (CPU_Trap_table_entry *) u32_tbr;
194
195  slot = &tbr[ real_vector ];
196
197  /*
198   *  Get the address of the old_handler from the trap table.
199   *
200   *  NOTE: The old_handler returned will be bogus if it does not follow
201   *        the RTEMS model.
202   */
203
204#define HIGH_BITS_MASK   0xFFFFFC00
205#define HIGH_BITS_SHIFT  10
206#define LOW_BITS_MASK    0x000003FF
207
208  if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
209    u32_handler = 
210      ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) |
211      (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
212    *old_handler = (proc_ptr) u32_handler;
213  } else
214    *old_handler = 0;
215
216  /*
217   *  Copy the template to the slot and then fix it.
218   */
219
220  *slot = _CPU_Trap_slot_template;
221
222  u32_handler = (unsigned32) new_handler;
223
224  slot->mov_vector_l3 |= vector;
225  slot->sethi_of_handler_to_l4 |= 
226    (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
227  slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
228
229  /* need to flush icache after this !!! */
230
231  rtems_cache_invalidate_entire_instruction();
232
233}
234
235/*PAGE
236 *
237 *  _CPU_ISR_install_vector
238 *
239 *  This kernel routine installs the RTEMS handler for the
240 *  specified vector.
241 *
242 *  Input parameters:
243 *    vector       - interrupt vector number
244 *    new_handler  - replacement ISR for this vector number
245 *    old_handler  - pointer to former ISR for this vector number
246 *
247 *  Output parameters:
248 *    *old_handler - former ISR for this vector number
249 *
250 */
251
252void _CPU_ISR_install_vector(
253  unsigned32  vector,
254  proc_ptr    new_handler,
255  proc_ptr   *old_handler
256)
257{
258   unsigned32 real_vector;
259   proc_ptr   ignored;
260
261  /*
262   *  Get the "real" trap number for this vector ignoring the synchronous
263   *  versus asynchronous indicator included with our vector numbers.
264   */
265
266   real_vector = SPARC_REAL_TRAP_NUMBER( vector );
267
268   /*
269    *  Return the previous ISR handler.
270    */
271
272   *old_handler = _ISR_Vector_table[ real_vector ];
273
274   /*
275    *  Install the wrapper so this ISR can be invoked properly.
276    */
277
278   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
279
280   /*
281    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
282    *  be used by the _ISR_Handler so the user gets control.
283    */
284
285    _ISR_Vector_table[ real_vector ] = new_handler;
286}
287
288/*PAGE
289 *
290 *  _CPU_Context_Initialize
291 *
292 *  This kernel routine initializes the basic non-FP context area associated
293 *  with each thread.
294 *
295 *  Input parameters:
296 *    the_context  - pointer to the context area
297 *    stack_base   - address of memory for the SPARC
298 *    size         - size in bytes of the stack area
299 *    new_level    - interrupt level for this context area
300 *    entry_point  - the starting execution point for this this context
301 *    is_fp        - TRUE if this context is associated with an FP thread
302 *
303 *  Output parameters: NONE
304 */
305
306void _CPU_Context_Initialize(
307  Context_Control  *the_context,
308  unsigned32       *stack_base,
309  unsigned32        size,
310  unsigned32        new_level,
311  void             *entry_point,
312  boolean           is_fp
313)
314{
315    unsigned32   stack_high;  /* highest "stack aligned" address */
316    unsigned32   the_size;
317    unsigned32   tmp_psr;
318 
319    /*
320     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
321     *  based on the stack_high address. 
322     */
323 
324    stack_high = ((unsigned32)(stack_base) + size);
325    stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
326 
327    the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
328 
329    /*
330     *  See the README in this directory for a diagram of the stack.
331     */
332 
333    the_context->o7    = ((unsigned32) entry_point) - 8;
334    the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
335    the_context->i6_fp = stack_high;
336
337    /*
338     *  Build the PSR for the task.  Most everything can be 0 and the
339     *  CWP is corrected during the context switch.
340     *
341     *  The EF bit determines if the floating point unit is available.
342     *  The FPU is ONLY enabled if the context is associated with an FP task
343     *  and this SPARC model has an FPU.
344     */
345
346    sparc_get_psr( tmp_psr );
347    tmp_psr &= ~SPARC_PSR_PIL_MASK;
348    tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
349    tmp_psr &= ~SPARC_PSR_EF_MASK;      /* disabled by default */
350   
351#if (SPARC_HAS_FPU == 1)
352    /*
353     *  If this bit is not set, then a task gets a fault when it accesses
354     *  a floating point register.  This is a nice way to detect floating
355     *  point tasks which are not currently declared as such.
356     */
357
358    if ( is_fp )
359      tmp_psr |= SPARC_PSR_EF_MASK;
360#endif
361    the_context->psr = tmp_psr;
362}
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