source: rtems/cpukit/score/cpu/sparc/cpu.c @ 21c468b

4.104.114.84.9
Last change on this file since 21c468b was 21c468b, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 29, 2002 at 2:17:58 PM

2002-03-28 Ralf Corsepius <corsepiu@…>

  • cpu.c: Replace NO_TABLE_MOVE-support by external function (code moved to libcpu/sparc/tbr/tbr.c).
  • cpu.h: Replace NO_TABLE_MOVE-support by external function (code moved to libcpu/sparc/tbr/tbr.h).
  • sparc.h: Add sparc_init_tbr (implemented in libcpu/sparc/tbr/tbr.c).
  • Property mode set to 100644
File size: 9.0 KB
Line 
1/*
2 *  SPARC Dependent Source
3 *
4 *  COPYRIGHT (c) 1989-1999.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 *  $Id$
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16#include <rtems/rtems/cache.h>
17
18/*
19 *  This initializes the set of opcodes placed in each trap
20 *  table entry.  The routine which installs a handler is responsible
21 *  for filling in the fields for the _handler address and the _vector
22 *  trap type.
23 *
24 *  The constants following this structure are masks for the fields which
25 *  must be filled in when the handler is installed.
26 */
27
28const CPU_Trap_table_entry _CPU_Trap_slot_template = {
29  0xa1480000,      /* mov   %psr, %l0           */
30  0x29000000,      /* sethi %hi(_handler), %l4  */
31  0x81c52000,      /* jmp   %l4 + %lo(_handler) */
32  0xa6102000       /* mov   _vector, %l3        */
33};
34
35/*PAGE
36 *
37 *  _CPU_Initialize
38 *
39 *  This routine performs processor dependent initialization.
40 *
41 *  Input Parameters:
42 *    cpu_table       - CPU table to initialize
43 *    thread_dispatch - address of disptaching routine
44 *
45 *  Output Parameters: NONE
46 *
47 *  NOTE: There is no need to save the pointer to the thread dispatch routine.
48 *        The SPARC's assembly code can reference it directly with no problems.
49 */
50
51void _CPU_Initialize(
52  rtems_cpu_table  *cpu_table,
53  void            (*thread_dispatch)      /* ignored on this CPU */
54)
55{
56  void                  *pointer;
57
58  sparc_init_tbr();
59 
60#if (SPARC_HAS_FPU == 1)
61
62  /*
63   *  This seems to be the most appropriate way to obtain an initial
64   *  FP context on the SPARC.  The NULL fp context is copied it to
65   *  the task's FP context during Context_Initialize.
66   */
67
68  pointer = &_CPU_Null_fp_context;
69  _CPU_Context_save_fp( &pointer );
70#endif
71
72  /*
73   *  Grab our own copy of the user's CPU table.
74   */
75
76  _CPU_Table = *cpu_table;
77}
78
79/*PAGE
80 *
81 *  _CPU_ISR_Get_level
82 *
83 *  Input Parameters: NONE
84 *
85 *  Output Parameters:
86 *    returns the current interrupt level (PIL field of the PSR)
87 */
88 
89unsigned32 _CPU_ISR_Get_level( void )
90{
91  unsigned32 level;
92 
93  sparc_get_interrupt_level( level );
94 
95  return level;
96}
97
98/*PAGE
99 *
100 *  _CPU_ISR_install_raw_handler
101 *
102 *  This routine installs the specified handler as a "raw" non-executive
103 *  supported trap handler (a.k.a. interrupt service routine).
104 *
105 *  Input Parameters:
106 *    vector      - trap table entry number plus synchronous
107 *                    vs. asynchronous information
108 *    new_handler - address of the handler to be installed
109 *    old_handler - pointer to an address of the handler previously installed
110 *
111 *  Output Parameters: NONE
112 *    *new_handler - address of the handler previously installed
113 *
114 *  NOTE:
115 *
116 *  On the SPARC, there are really only 256 vectors.  However, the executive
117 *  has no easy, fast, reliable way to determine which traps are synchronous
118 *  and which are asynchronous.  By default, synchronous traps return to the
119 *  instruction which caused the interrupt.  So if you install a software
120 *  trap handler as an executive interrupt handler (which is desirable since
121 *  RTEMS takes care of window and register issues), then the executive needs
122 *  to know that the return address is to the trap rather than the instruction
123 *  following the trap.
124 *
125 *  So vectors 0 through 255 are treated as regular asynchronous traps which
126 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
127 *  by the executive to be synchronous and to require that the return address
128 *  be fudged.
129 *
130 *  If you use this mechanism to install a trap handler which must reexecute
131 *  the instruction which caused the trap, then it should be installed as
132 *  an asynchronous trap.  This will avoid the executive changing the return
133 *  address.
134 */
135 
136void _CPU_ISR_install_raw_handler(
137  unsigned32  vector,
138  proc_ptr    new_handler,
139  proc_ptr   *old_handler
140)
141{
142  unsigned32             real_vector;
143  CPU_Trap_table_entry  *tbr;
144  CPU_Trap_table_entry  *slot;
145  unsigned32             u32_tbr;
146  unsigned32             u32_handler;
147
148  /*
149   *  Get the "real" trap number for this vector ignoring the synchronous
150   *  versus asynchronous indicator included with our vector numbers.
151   */
152
153  real_vector = SPARC_REAL_TRAP_NUMBER( vector );
154
155  /*
156   *  Get the current base address of the trap table and calculate a pointer
157   *  to the slot we are interested in.
158   */
159
160  sparc_get_tbr( u32_tbr );
161
162  u32_tbr &= 0xfffff000;
163
164  tbr = (CPU_Trap_table_entry *) u32_tbr;
165
166  slot = &tbr[ real_vector ];
167
168  /*
169   *  Get the address of the old_handler from the trap table.
170   *
171   *  NOTE: The old_handler returned will be bogus if it does not follow
172   *        the RTEMS model.
173   */
174
175#define HIGH_BITS_MASK   0xFFFFFC00
176#define HIGH_BITS_SHIFT  10
177#define LOW_BITS_MASK    0x000003FF
178
179  if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
180    u32_handler = 
181      ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) |
182      (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
183    *old_handler = (proc_ptr) u32_handler;
184  } else
185    *old_handler = 0;
186
187  /*
188   *  Copy the template to the slot and then fix it.
189   */
190
191  *slot = _CPU_Trap_slot_template;
192
193  u32_handler = (unsigned32) new_handler;
194
195  slot->mov_vector_l3 |= vector;
196  slot->sethi_of_handler_to_l4 |= 
197    (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
198  slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
199
200  /* need to flush icache after this !!! */
201
202  rtems_cache_invalidate_entire_instruction();
203
204}
205
206/*PAGE
207 *
208 *  _CPU_ISR_install_vector
209 *
210 *  This kernel routine installs the RTEMS handler for the
211 *  specified vector.
212 *
213 *  Input parameters:
214 *    vector       - interrupt vector number
215 *    new_handler  - replacement ISR for this vector number
216 *    old_handler  - pointer to former ISR for this vector number
217 *
218 *  Output parameters:
219 *    *old_handler - former ISR for this vector number
220 *
221 */
222
223void _CPU_ISR_install_vector(
224  unsigned32  vector,
225  proc_ptr    new_handler,
226  proc_ptr   *old_handler
227)
228{
229   unsigned32 real_vector;
230   proc_ptr   ignored;
231
232  /*
233   *  Get the "real" trap number for this vector ignoring the synchronous
234   *  versus asynchronous indicator included with our vector numbers.
235   */
236
237   real_vector = SPARC_REAL_TRAP_NUMBER( vector );
238
239   /*
240    *  Return the previous ISR handler.
241    */
242
243   *old_handler = _ISR_Vector_table[ real_vector ];
244
245   /*
246    *  Install the wrapper so this ISR can be invoked properly.
247    */
248
249   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
250
251   /*
252    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
253    *  be used by the _ISR_Handler so the user gets control.
254    */
255
256    _ISR_Vector_table[ real_vector ] = new_handler;
257}
258
259/*PAGE
260 *
261 *  _CPU_Context_Initialize
262 *
263 *  This kernel routine initializes the basic non-FP context area associated
264 *  with each thread.
265 *
266 *  Input parameters:
267 *    the_context  - pointer to the context area
268 *    stack_base   - address of memory for the SPARC
269 *    size         - size in bytes of the stack area
270 *    new_level    - interrupt level for this context area
271 *    entry_point  - the starting execution point for this this context
272 *    is_fp        - TRUE if this context is associated with an FP thread
273 *
274 *  Output parameters: NONE
275 */
276
277void _CPU_Context_Initialize(
278  Context_Control  *the_context,
279  unsigned32       *stack_base,
280  unsigned32        size,
281  unsigned32        new_level,
282  void             *entry_point,
283  boolean           is_fp
284)
285{
286    unsigned32   stack_high;  /* highest "stack aligned" address */
287    unsigned32   the_size;
288    unsigned32   tmp_psr;
289 
290    /*
291     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
292     *  based on the stack_high address. 
293     */
294 
295    stack_high = ((unsigned32)(stack_base) + size);
296    stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
297 
298    the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
299 
300    /*
301     *  See the README in this directory for a diagram of the stack.
302     */
303 
304    the_context->o7    = ((unsigned32) entry_point) - 8;
305    the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
306    the_context->i6_fp = stack_high;
307
308    /*
309     *  Build the PSR for the task.  Most everything can be 0 and the
310     *  CWP is corrected during the context switch.
311     *
312     *  The EF bit determines if the floating point unit is available.
313     *  The FPU is ONLY enabled if the context is associated with an FP task
314     *  and this SPARC model has an FPU.
315     */
316
317    sparc_get_psr( tmp_psr );
318    tmp_psr &= ~SPARC_PSR_PIL_MASK;
319    tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
320    tmp_psr &= ~SPARC_PSR_EF_MASK;      /* disabled by default */
321   
322#if (SPARC_HAS_FPU == 1)
323    /*
324     *  If this bit is not set, then a task gets a fault when it accesses
325     *  a floating point register.  This is a nice way to detect floating
326     *  point tasks which are not currently declared as such.
327     */
328
329    if ( is_fp )
330      tmp_psr |= SPARC_PSR_EF_MASK;
331#endif
332    the_context->psr = tmp_psr;
333}
Note: See TracBrowser for help on using the repository browser.