source: rtems/cpukit/score/cpu/sparc/cpu.c @ 08311cc3

4.104.114.84.95
Last change on this file since 08311cc3 was 08311cc3, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 17, 1999 at 5:51:34 PM

Updated copyright notice.

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1/*
2 *  SPARC Dependent Source
3 *
4 *  COPYRIGHT (c) 1989-1999.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
12 *  Research Corporation (OAR) under contract to the European Space
13 *  Agency (ESA).
14 *
15 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
16 *  European Space Agency.
17 *
18 *  $Id$
19 */
20
21#include <rtems/system.h>
22#include <rtems/score/isr.h>
23
24#if defined(erc32)
25#include <erc32.h>
26#endif
27
28/*
29 *  This initializes the set of opcodes placed in each trap
30 *  table entry.  The routine which installs a handler is responsible
31 *  for filling in the fields for the _handler address and the _vector
32 *  trap type.
33 *
34 *  The constants following this structure are masks for the fields which
35 *  must be filled in when the handler is installed.
36 */
37
38const CPU_Trap_table_entry _CPU_Trap_slot_template = {
39  0xa1480000,      /* mov   %psr, %l0           */
40  0x29000000,      /* sethi %hi(_handler), %l4  */
41  0x81c52000,      /* jmp   %l4 + %lo(_handler) */
42  0xa6102000       /* mov   _vector, %l3        */
43};
44
45/*PAGE
46 *
47 *  _CPU_Initialize
48 *
49 *  This routine performs processor dependent initialization.
50 *
51 *  Input Parameters:
52 *    cpu_table       - CPU table to initialize
53 *    thread_dispatch - address of disptaching routine
54 *
55 *  Output Parameters: NONE
56 *
57 *  NOTE: There is no need to save the pointer to the thread dispatch routine.
58 *        The SPARC's assembly code can reference it directly with no problems.
59 */
60
61void _CPU_Initialize(
62  rtems_cpu_table  *cpu_table,
63  void            (*thread_dispatch)      /* ignored on this CPU */
64)
65{
66  void                  *pointer;
67
68#ifndef NO_TABLE_MOVE
69  unsigned32             trap_table_start;
70  unsigned32             tbr_value;
71  CPU_Trap_table_entry  *old_tbr;
72  CPU_Trap_table_entry  *trap_table;
73
74  /*
75   *  Install the executive's trap table.  All entries from the original
76   *  trap table are copied into the executive's trap table.  This is essential
77   *  since this preserves critical trap handlers such as the window underflow
78   *  and overflow handlers.  It is the responsibility of the BSP to provide
79   *  install these in the initial trap table.
80   */
81
82 
83  trap_table_start = (unsigned32) &_CPU_Trap_Table_area;
84  if (trap_table_start & (SPARC_TRAP_TABLE_ALIGNMENT-1))
85    trap_table_start = (trap_table_start + SPARC_TRAP_TABLE_ALIGNMENT) & 
86                       ~(SPARC_TRAP_TABLE_ALIGNMENT-1);
87
88  trap_table = (CPU_Trap_table_entry *) trap_table_start;
89
90  sparc_get_tbr( tbr_value );
91
92  old_tbr = (CPU_Trap_table_entry *) (tbr_value & 0xfffff000);
93
94  memcpy( trap_table, (void *) old_tbr, 256 * sizeof( CPU_Trap_table_entry ) );
95
96  sparc_set_tbr( trap_table_start );
97
98#endif
99
100  /*
101   *  This seems to be the most appropriate way to obtain an initial
102   *  FP context on the SPARC.  The NULL fp context is copied it to
103   *  the task's FP context during Context_Initialize.
104   */
105
106  pointer = &_CPU_Null_fp_context;
107  _CPU_Context_save_fp( &pointer );
108
109  /*
110   *  Grab our own copy of the user's CPU table.
111   */
112
113  _CPU_Table = *cpu_table;
114
115#if defined(erc32)
116
117  /*
118   *  ERC32 specific initialization
119   */
120
121  _ERC32_MEC_Timer_Control_Mirror = 0;
122  ERC32_MEC.Timer_Control = 0;
123
124  ERC32_MEC.Control |= ERC32_CONFIGURATION_POWER_DOWN_ALLOWED;
125
126#endif
127
128}
129
130/*PAGE
131 *
132 *  _CPU_ISR_Get_level
133 *
134 *  Input Parameters: NONE
135 *
136 *  Output Parameters:
137 *    returns the current interrupt level (PIL field of the PSR)
138 */
139 
140unsigned32 _CPU_ISR_Get_level( void )
141{
142  unsigned32 level;
143 
144  sparc_get_interrupt_level( level );
145 
146  return level;
147}
148
149/*PAGE
150 *
151 *  _CPU_ISR_install_raw_handler
152 *
153 *  This routine installs the specified handler as a "raw" non-executive
154 *  supported trap handler (a.k.a. interrupt service routine).
155 *
156 *  Input Parameters:
157 *    vector      - trap table entry number plus synchronous
158 *                    vs. asynchronous information
159 *    new_handler - address of the handler to be installed
160 *    old_handler - pointer to an address of the handler previously installed
161 *
162 *  Output Parameters: NONE
163 *    *new_handler - address of the handler previously installed
164 *
165 *  NOTE:
166 *
167 *  On the SPARC, there are really only 256 vectors.  However, the executive
168 *  has no easy, fast, reliable way to determine which traps are synchronous
169 *  and which are asynchronous.  By default, synchronous traps return to the
170 *  instruction which caused the interrupt.  So if you install a software
171 *  trap handler as an executive interrupt handler (which is desirable since
172 *  RTEMS takes care of window and register issues), then the executive needs
173 *  to know that the return address is to the trap rather than the instruction
174 *  following the trap.
175 *
176 *  So vectors 0 through 255 are treated as regular asynchronous traps which
177 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
178 *  by the executive to be synchronous and to require that the return address
179 *  be fudged.
180 *
181 *  If you use this mechanism to install a trap handler which must reexecute
182 *  the instruction which caused the trap, then it should be installed as
183 *  an asynchronous trap.  This will avoid the executive changing the return
184 *  address.
185 */
186 
187void _CPU_ISR_install_raw_handler(
188  unsigned32  vector,
189  proc_ptr    new_handler,
190  proc_ptr   *old_handler
191)
192{
193  unsigned32             real_vector;
194  CPU_Trap_table_entry  *tbr;
195  CPU_Trap_table_entry  *slot;
196  unsigned32             u32_tbr;
197  unsigned32             u32_handler;
198
199  /*
200   *  Get the "real" trap number for this vector ignoring the synchronous
201   *  versus asynchronous indicator included with our vector numbers.
202   */
203
204  real_vector = SPARC_REAL_TRAP_NUMBER( vector );
205
206  /*
207   *  Get the current base address of the trap table and calculate a pointer
208   *  to the slot we are interested in.
209   */
210
211  sparc_get_tbr( u32_tbr );
212
213  u32_tbr &= 0xfffff000;
214
215  tbr = (CPU_Trap_table_entry *) u32_tbr;
216
217  slot = &tbr[ real_vector ];
218
219  /*
220   *  Get the address of the old_handler from the trap table.
221   *
222   *  NOTE: The old_handler returned will be bogus if it does not follow
223   *        the RTEMS model.
224   */
225
226#define HIGH_BITS_MASK   0xFFFFFC00
227#define HIGH_BITS_SHIFT  10
228#define LOW_BITS_MASK    0x000003FF
229
230  if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
231    u32_handler = 
232      ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) |
233      (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
234    *old_handler = (proc_ptr) u32_handler;
235  } else
236    *old_handler = 0;
237
238  /*
239   *  Copy the template to the slot and then fix it.
240   */
241
242  *slot = _CPU_Trap_slot_template;
243
244  u32_handler = (unsigned32) new_handler;
245
246  slot->mov_vector_l3 |= vector;
247  slot->sethi_of_handler_to_l4 |= 
248    (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
249  slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
250}
251
252/*PAGE
253 *
254 *  _CPU_ISR_install_vector
255 *
256 *  This kernel routine installs the RTEMS handler for the
257 *  specified vector.
258 *
259 *  Input parameters:
260 *    vector       - interrupt vector number
261 *    new_handler  - replacement ISR for this vector number
262 *    old_handler  - pointer to former ISR for this vector number
263 *
264 *  Output parameters:
265 *    *old_handler - former ISR for this vector number
266 *
267 */
268
269void _CPU_ISR_install_vector(
270  unsigned32  vector,
271  proc_ptr    new_handler,
272  proc_ptr   *old_handler
273)
274{
275   unsigned32 real_vector;
276   proc_ptr   ignored;
277
278  /*
279   *  Get the "real" trap number for this vector ignoring the synchronous
280   *  versus asynchronous indicator included with our vector numbers.
281   */
282
283   real_vector = SPARC_REAL_TRAP_NUMBER( vector );
284
285   /*
286    *  Return the previous ISR handler.
287    */
288
289   *old_handler = _ISR_Vector_table[ real_vector ];
290
291   /*
292    *  Install the wrapper so this ISR can be invoked properly.
293    */
294
295   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
296
297   /*
298    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
299    *  be used by the _ISR_Handler so the user gets control.
300    */
301
302    _ISR_Vector_table[ real_vector ] = new_handler;
303}
304
305/*PAGE
306 *
307 *  _CPU_Context_Initialize
308 *
309 *  This kernel routine initializes the basic non-FP context area associated
310 *  with each thread.
311 *
312 *  Input parameters:
313 *    the_context  - pointer to the context area
314 *    stack_base   - address of memory for the SPARC
315 *    size         - size in bytes of the stack area
316 *    new_level    - interrupt level for this context area
317 *    entry_point  - the starting execution point for this this context
318 *    is_fp        - TRUE if this context is associated with an FP thread
319 *
320 *  Output parameters: NONE
321 */
322
323void _CPU_Context_Initialize(
324  Context_Control  *the_context,
325  unsigned32       *stack_base,
326  unsigned32        size,
327  unsigned32        new_level,
328  void             *entry_point,
329  boolean           is_fp
330)
331{
332    unsigned32   stack_high;  /* highest "stack aligned" address */
333    unsigned32   the_size;
334    unsigned32   tmp_psr;
335 
336    /*
337     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
338     *  based on the stack_high address. 
339     */
340 
341    stack_high = ((unsigned32)(stack_base) + size);
342    stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
343 
344    the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
345 
346    /*
347     *  See the README in this directory for a diagram of the stack.
348     */
349 
350    the_context->o7    = ((unsigned32) entry_point) - 8;
351    the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
352    the_context->i6_fp = stack_high;
353
354    /*
355     *  Build the PSR for the task.  Most everything can be 0 and the
356     *  CWP is corrected during the context switch.
357     *
358     *  The EF bit determines if the floating point unit is available.
359     *  The FPU is ONLY enabled if the context is associated with an FP task
360     *  and this SPARC model has an FPU.
361     */
362
363    sparc_get_psr( tmp_psr );
364    tmp_psr &= ~SPARC_PSR_PIL_MASK;
365    tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
366    tmp_psr &= ~SPARC_PSR_EF_MASK;      /* disabled by default */
367   
368#if (SPARC_HAS_FPU == 1)
369    /*
370     *  If this bit is not set, then a task gets a fault when it accesses
371     *  a floating point register.  This is a nice way to detect floating
372     *  point tasks which are not currently declared as such.
373     */
374
375    if ( is_fp )
376      tmp_psr |= SPARC_PSR_EF_MASK;
377#endif
378    the_context->psr = tmp_psr;
379}
380
381/*PAGE
382 *
383 *  _CPU_Thread_Idle_body
384 *
385 *  Some SPARC implementations have low power, sleep, or idle modes.  This
386 *  tries to take advantage of those models. 
387 */
388 
389#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
390
391/*
392 *  This is the implementation for the erc32.
393 *
394 *  NOTE: Low power mode was enabled at initialization time.
395 */
396
397#if defined(erc32)
398
399void _CPU_Thread_Idle_body( void )
400{
401  while (1) {
402    ERC32_MEC.Power_Down = 0;   /* value is irrelevant */
403  }
404}
405
406#endif
407
408#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
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