1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief SPARC CPU Dependent Source |
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5 | */ |
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6 | |
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7 | /* |
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8 | * COPYRIGHT (c) 1989-2007. |
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9 | * On-Line Applications Research Corporation (OAR). |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.com/license/LICENSE. |
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14 | */ |
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15 | |
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16 | #ifdef HAVE_CONFIG_H |
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17 | #include "config.h" |
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18 | #endif |
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19 | |
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20 | #include <rtems/system.h> |
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21 | #include <rtems/score/isr.h> |
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22 | #include <rtems/score/percpu.h> |
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23 | #include <rtems/score/tls.h> |
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24 | #include <rtems/rtems/cache.h> |
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25 | |
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26 | RTEMS_STATIC_ASSERT( |
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27 | offsetof( Per_CPU_Control, cpu_per_cpu.isr_dispatch_disable) |
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28 | == SPARC_PER_CPU_ISR_DISPATCH_DISABLE, |
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29 | SPARC_PER_CPU_ISR_DISPATCH_DISABLE |
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30 | ); |
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31 | |
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32 | /* |
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33 | * This initializes the set of opcodes placed in each trap |
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34 | * table entry. The routine which installs a handler is responsible |
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35 | * for filling in the fields for the _handler address and the _vector |
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36 | * trap type. |
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37 | * |
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38 | * The constants following this structure are masks for the fields which |
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39 | * must be filled in when the handler is installed. |
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40 | */ |
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41 | |
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42 | const CPU_Trap_table_entry _CPU_Trap_slot_template = { |
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43 | 0xa1480000, /* mov %psr, %l0 */ |
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44 | 0x29000000, /* sethi %hi(_handler), %l4 */ |
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45 | 0x81c52000, /* jmp %l4 + %lo(_handler) */ |
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46 | 0xa6102000 /* mov _vector, %l3 */ |
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47 | }; |
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48 | |
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49 | /* |
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50 | * _CPU_Initialize |
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51 | * |
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52 | * This routine performs processor dependent initialization. |
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53 | * |
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54 | * INPUT PARAMETERS: NONE |
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55 | * |
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56 | * Output Parameters: NONE |
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57 | * |
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58 | * NOTE: There is no need to save the pointer to the thread dispatch routine. |
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59 | * The SPARC's assembly code can reference it directly with no problems. |
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60 | */ |
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61 | |
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62 | void _CPU_Initialize(void) |
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63 | { |
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64 | #if (SPARC_HAS_FPU == 1) |
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65 | Context_Control_fp *pointer; |
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66 | |
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67 | /* |
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68 | * This seems to be the most appropriate way to obtain an initial |
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69 | * FP context on the SPARC. The NULL fp context is copied it to |
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70 | * the task's FP context during Context_Initialize. |
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71 | */ |
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72 | |
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73 | pointer = &_CPU_Null_fp_context; |
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74 | _CPU_Context_save_fp( &pointer ); |
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75 | #endif |
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76 | } |
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77 | |
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78 | uint32_t _CPU_ISR_Get_level( void ) |
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79 | { |
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80 | uint32_t level; |
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81 | |
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82 | sparc_get_interrupt_level( level ); |
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83 | |
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84 | return level; |
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85 | } |
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86 | |
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87 | /* |
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88 | * _CPU_ISR_install_raw_handler |
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89 | * |
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90 | * This routine installs the specified handler as a "raw" non-executive |
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91 | * supported trap handler (a.k.a. interrupt service routine). |
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92 | * |
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93 | * Input Parameters: |
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94 | * vector - trap table entry number plus synchronous |
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95 | * vs. asynchronous information |
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96 | * new_handler - address of the handler to be installed |
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97 | * old_handler - pointer to an address of the handler previously installed |
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98 | * |
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99 | * Output Parameters: NONE |
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100 | * *new_handler - address of the handler previously installed |
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101 | * |
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102 | * NOTE: |
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103 | * |
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104 | * On the SPARC, there are really only 256 vectors. However, the executive |
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105 | * has no easy, fast, reliable way to determine which traps are synchronous |
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106 | * and which are asynchronous. By default, synchronous traps return to the |
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107 | * instruction which caused the interrupt. So if you install a software |
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108 | * trap handler as an executive interrupt handler (which is desirable since |
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109 | * RTEMS takes care of window and register issues), then the executive needs |
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110 | * to know that the return address is to the trap rather than the instruction |
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111 | * following the trap. |
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112 | * |
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113 | * So vectors 0 through 255 are treated as regular asynchronous traps which |
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114 | * provide the "correct" return address. Vectors 256 through 512 are assumed |
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115 | * by the executive to be synchronous and to require that the return address |
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116 | * be fudged. |
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117 | * |
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118 | * If you use this mechanism to install a trap handler which must reexecute |
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119 | * the instruction which caused the trap, then it should be installed as |
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120 | * an asynchronous trap. This will avoid the executive changing the return |
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121 | * address. |
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122 | */ |
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123 | |
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124 | void _CPU_ISR_install_raw_handler( |
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125 | uint32_t vector, |
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126 | proc_ptr new_handler, |
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127 | proc_ptr *old_handler |
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128 | ) |
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129 | { |
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130 | uint32_t real_vector; |
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131 | CPU_Trap_table_entry *tbr; |
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132 | CPU_Trap_table_entry *slot; |
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133 | uint32_t u32_tbr; |
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134 | uint32_t u32_handler; |
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135 | |
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136 | /* |
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137 | * Get the "real" trap number for this vector ignoring the synchronous |
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138 | * versus asynchronous indicator included with our vector numbers. |
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139 | */ |
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140 | |
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141 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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142 | |
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143 | /* |
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144 | * Get the current base address of the trap table and calculate a pointer |
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145 | * to the slot we are interested in. |
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146 | */ |
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147 | |
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148 | sparc_get_tbr( u32_tbr ); |
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149 | |
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150 | u32_tbr &= 0xfffff000; |
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151 | |
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152 | tbr = (CPU_Trap_table_entry *) u32_tbr; |
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153 | |
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154 | slot = &tbr[ real_vector ]; |
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155 | |
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156 | /* |
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157 | * Get the address of the old_handler from the trap table. |
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158 | * |
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159 | * NOTE: The old_handler returned will be bogus if it does not follow |
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160 | * the RTEMS model. |
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161 | */ |
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162 | |
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163 | #define HIGH_BITS_MASK 0xFFFFFC00 |
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164 | #define HIGH_BITS_SHIFT 10 |
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165 | #define LOW_BITS_MASK 0x000003FF |
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166 | |
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167 | if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) { |
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168 | u32_handler = |
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169 | (slot->sethi_of_handler_to_l4 << HIGH_BITS_SHIFT) | |
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170 | (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK); |
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171 | *old_handler = (proc_ptr) u32_handler; |
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172 | } else |
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173 | *old_handler = 0; |
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174 | |
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175 | /* |
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176 | * Copy the template to the slot and then fix it. |
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177 | */ |
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178 | |
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179 | *slot = _CPU_Trap_slot_template; |
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180 | |
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181 | u32_handler = (uint32_t) new_handler; |
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182 | |
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183 | slot->mov_vector_l3 |= vector; |
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184 | slot->sethi_of_handler_to_l4 |= |
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185 | (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT; |
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186 | slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK); |
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187 | |
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188 | /* need to flush icache after this !!! */ |
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189 | |
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190 | rtems_cache_invalidate_entire_instruction(); |
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191 | |
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192 | } |
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193 | |
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194 | void _CPU_ISR_install_vector( |
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195 | uint32_t vector, |
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196 | proc_ptr new_handler, |
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197 | proc_ptr *old_handler |
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198 | ) |
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199 | { |
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200 | uint32_t real_vector; |
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201 | proc_ptr ignored; |
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202 | |
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203 | /* |
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204 | * Get the "real" trap number for this vector ignoring the synchronous |
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205 | * versus asynchronous indicator included with our vector numbers. |
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206 | */ |
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207 | |
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208 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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209 | |
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210 | /* |
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211 | * Return the previous ISR handler. |
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212 | */ |
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213 | |
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214 | *old_handler = _ISR_Vector_table[ real_vector ]; |
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215 | |
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216 | /* |
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217 | * Install the wrapper so this ISR can be invoked properly. |
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218 | */ |
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219 | |
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220 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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221 | |
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222 | /* |
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223 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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224 | * be used by the _ISR_Handler so the user gets control. |
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225 | */ |
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226 | |
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227 | _ISR_Vector_table[ real_vector ] = new_handler; |
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228 | } |
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229 | |
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230 | void _CPU_Context_Initialize( |
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231 | Context_Control *the_context, |
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232 | uint32_t *stack_base, |
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233 | uint32_t size, |
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234 | uint32_t new_level, |
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235 | void *entry_point, |
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236 | bool is_fp, |
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237 | void *tls_area |
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238 | ) |
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239 | { |
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240 | uint32_t stack_high; /* highest "stack aligned" address */ |
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241 | uint32_t tmp_psr; |
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242 | |
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243 | /* |
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244 | * On CPUs with stacks which grow down (i.e. SPARC), we build the stack |
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245 | * based on the stack_high address. |
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246 | */ |
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247 | |
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248 | stack_high = ((uint32_t)(stack_base) + size); |
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249 | stack_high &= ~(CPU_STACK_ALIGNMENT - 1); |
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250 | |
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251 | /* |
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252 | * See the README in this directory for a diagram of the stack. |
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253 | */ |
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254 | |
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255 | the_context->o7 = ((uint32_t) entry_point) - 8; |
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256 | the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE; |
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257 | the_context->i6_fp = 0; |
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258 | |
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259 | /* |
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260 | * Build the PSR for the task. Most everything can be 0 and the |
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261 | * CWP is corrected during the context switch. |
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262 | * |
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263 | * The EF bit determines if the floating point unit is available. |
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264 | * The FPU is ONLY enabled if the context is associated with an FP task |
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265 | * and this SPARC model has an FPU. |
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266 | */ |
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267 | |
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268 | sparc_get_psr( tmp_psr ); |
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269 | tmp_psr &= ~SPARC_PSR_PIL_MASK; |
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270 | tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK; |
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271 | tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */ |
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272 | |
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273 | #if (SPARC_HAS_FPU == 1) |
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274 | /* |
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275 | * If this bit is not set, then a task gets a fault when it accesses |
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276 | * a floating point register. This is a nice way to detect floating |
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277 | * point tasks which are not currently declared as such. |
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278 | */ |
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279 | |
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280 | if ( is_fp ) |
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281 | tmp_psr |= SPARC_PSR_EF_MASK; |
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282 | #endif |
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283 | the_context->psr = tmp_psr; |
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284 | |
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285 | /* |
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286 | * Since THIS thread is being created, there is no way that THIS |
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287 | * thread can have an _ISR_Dispatch stack frame on its stack. |
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288 | */ |
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289 | the_context->isr_dispatch_disable = 0; |
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290 | |
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291 | if ( tls_area != NULL ) { |
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292 | void *tcb = _TLS_TCB_after_tls_block_initialize( tls_area ); |
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293 | |
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294 | the_context->g7 = (uintptr_t) tcb; |
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295 | } |
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296 | } |
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