[c62d36f] | 1 | /* |
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| 2 | * SPARC Dependent Source |
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| 3 | * |
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| 4 | * $Id$ |
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| 5 | */ |
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| 6 | |
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| 7 | #include <rtems/system.h> |
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| 8 | #include <rtems/score/isr.h> |
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| 9 | |
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| 10 | /* _CPU_Initialize |
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| 11 | * |
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| 12 | * This routine performs processor dependent initialization. |
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| 13 | * |
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| 14 | * INPUT PARAMETERS: |
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| 15 | * cpu_table - CPU table to initialize |
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| 16 | * thread_dispatch - address of disptaching routine |
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| 17 | */ |
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| 18 | |
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| 19 | |
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| 20 | void _CPU_Initialize( |
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| 21 | rtems_cpu_table *cpu_table, |
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| 22 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 23 | ) |
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| 24 | { |
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| 25 | void *pointer; |
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| 26 | |
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| 27 | /* |
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| 28 | * The thread_dispatch argument is the address of the entry point |
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| 29 | * for the routine called at the end of an ISR once it has been |
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| 30 | * decided a context switch is necessary. On some compilation |
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| 31 | * systems it is difficult to call a high-level language routine |
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| 32 | * from assembly. This allows us to trick these systems. |
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| 33 | * |
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| 34 | * If you encounter this problem save the entry point in a CPU |
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| 35 | * dependent variable. |
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| 36 | */ |
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| 37 | |
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| 38 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
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| 39 | |
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| 40 | /* |
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| 41 | * If there is not an easy way to initialize the FP context |
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| 42 | * during Context_Initialize, then it is usually easier to |
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| 43 | * save an "uninitialized" FP context here and copy it to |
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| 44 | * the task's during Context_Initialize. |
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| 45 | */ |
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| 46 | |
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| 47 | pointer = &_CPU_Null_fp_context; |
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| 48 | _CPU_Context_save_fp( &pointer ); |
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| 49 | |
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| 50 | _CPU_Table = *cpu_table; |
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| 51 | } |
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| 52 | |
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| 53 | /*PAGE |
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| 54 | * |
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| 55 | * _CPU_ISR_Get_level |
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| 56 | */ |
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| 57 | |
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| 58 | unsigned32 _CPU_ISR_Get_level( void ) |
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| 59 | { |
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| 60 | unsigned32 level; |
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| 61 | |
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| 62 | sparc_get_interrupt_level( level ); |
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| 63 | |
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| 64 | return level; |
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| 65 | } |
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| 66 | |
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| 67 | /* _CPU_ISR_install_vector |
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| 68 | * |
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| 69 | * This kernel routine installs the RTEMS handler for the |
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| 70 | * specified vector. |
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| 71 | * |
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| 72 | * Input parameters: |
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| 73 | * vector - interrupt vector number |
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| 74 | * old_handler - former ISR for this vector number |
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| 75 | * new_handler - replacement ISR for this vector number |
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| 76 | * |
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| 77 | * Output parameters: NONE |
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| 78 | * |
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| 79 | */ |
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| 80 | |
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| 81 | |
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| 82 | void _CPU_ISR_install_vector( |
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| 83 | unsigned32 vector, |
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| 84 | proc_ptr new_handler, |
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| 85 | proc_ptr *old_handler |
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| 86 | ) |
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| 87 | { |
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| 88 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 89 | |
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| 90 | /* |
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| 91 | * If the interrupt vector table is a table of pointer to isr entry |
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| 92 | * points, then we need to install the appropriate RTEMS interrupt |
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| 93 | * handler for this vector number. |
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| 94 | */ |
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| 95 | |
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| 96 | /* |
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| 97 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 98 | * be used by the _ISR_Handler so the user gets control. |
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| 99 | */ |
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| 100 | |
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| 101 | _ISR_Vector_table[ vector ] = new_handler; |
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| 102 | } |
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| 103 | |
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| 104 | /*PAGE |
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| 105 | * |
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| 106 | * _CPU_Install_interrupt_stack |
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| 107 | */ |
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| 108 | |
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| 109 | void _CPU_Install_interrupt_stack( void ) |
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| 110 | { |
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| 111 | } |
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| 112 | |
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| 113 | /*PAGE |
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| 114 | * |
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| 115 | * _CPU_Context_Initialize |
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| 116 | */ |
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| 117 | |
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| 118 | /* |
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| 119 | * The following constants assist in building a thread's initial context. |
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| 120 | */ |
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| 121 | |
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| 122 | #define CPU_FRAME_SIZE (112) /* based on disassembled test code */ |
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| 123 | #define ADDR_ADJ_OFFSET -8 |
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| 124 | |
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| 125 | void _CPU_Context_Initialize( |
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| 126 | Context_Control *_the_context, |
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| 127 | unsigned32 *_stack_base, |
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| 128 | unsigned32 _size, |
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| 129 | unsigned32 _new_level, |
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| 130 | void *_entry_point |
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| 131 | ) |
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| 132 | { |
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| 133 | unsigned32 jmp_addr; |
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| 134 | unsigned32 _stack_high; /* highest "stack aligned" address */ |
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| 135 | unsigned32 _the_size; |
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| 136 | unsigned32 tmp_psr; |
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| 137 | |
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| 138 | jmp_addr = (unsigned32) _entry_point; |
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| 139 | |
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| 140 | /* |
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| 141 | * On CPUs with stacks which grow down (i.e. SPARC), we build the stack |
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| 142 | * based on the _stack_high address. |
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| 143 | */ |
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| 144 | |
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| 145 | _stack_high = ((unsigned32)(_stack_base) + _size); |
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| 146 | _stack_high &= ~(CPU_STACK_ALIGNMENT - 1); |
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| 147 | |
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| 148 | _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1); |
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| 149 | |
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| 150 | /* XXX following code is based on unix port */ |
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| 151 | /* |
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| 152 | * XXX SPARC port needs a diagram like this one... |
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| 153 | * See /usr/include/sys/stack.h in Solaris 2.3 for a nice |
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| 154 | * diagram of the stack. |
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| 155 | */ |
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| 156 | |
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| 157 | _the_context->o7 = jmp_addr + ADDR_ADJ_OFFSET; |
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| 158 | _the_context->o6 = (unsigned32)(_stack_high - CPU_FRAME_SIZE); |
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| 159 | _the_context->i6 = (unsigned32)(_stack_high); |
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| 160 | #if 0 |
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| 161 | _the_context->rp = jmp_addr + ADDR_ADJ_OFFSET; |
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| 162 | _the_context->sp = (unsigned32)(_stack_high - CPU_FRAME_SIZE); |
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| 163 | _the_context->fp = (unsigned32)(_stack_high); |
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| 164 | #endif |
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| 165 | |
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| 166 | _the_context->wim = 0x01; |
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| 167 | |
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| 168 | sparc_get_psr( tmp_psr ); |
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| 169 | tmp_psr &= ~SPARC_PIL_MASK; |
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| 170 | tmp_psr |= (((_new_level) << 8) & SPARC_PIL_MASK); |
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| 171 | tmp_psr = (tmp_psr & ~0x07) | 0x07; /* XXX should use num windows */ |
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| 172 | _the_context->psr = tmp_psr; |
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| 173 | } |
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| 174 | |
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| 175 | /*PAGE |
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| 176 | * |
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| 177 | * _CPU_Internal_threads_Idle_thread_body |
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| 178 | * |
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| 179 | * NOTES: |
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| 180 | * |
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| 181 | * 1. This is the same as the regular CPU independent algorithm. |
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| 182 | * |
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| 183 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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| 184 | * instruction, then don't forget to put it in an infinite loop. |
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| 185 | * |
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| 186 | * 3. Be warned. Some processors with onboard DMA have been known |
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| 187 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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| 188 | * also be a problem with other on-chip peripherals. So use this |
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| 189 | * hook with caution. |
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| 190 | */ |
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| 191 | |
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| 192 | void _CPU_Internal_threads_Idle_thread_body( void ) |
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| 193 | { |
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| 194 | |
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| 195 | for( ; ; ) |
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| 196 | /* insert your "halt" instruction here */ ; |
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| 197 | } |
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