[c62d36f] | 1 | /* |
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| 2 | * SPARC Dependent Source |
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| 3 | * |
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[08311cc3] | 4 | * COPYRIGHT (c) 1989-1999. |
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[c4808ca] | 5 | * On-Line Applications Research Corporation (OAR). |
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| 6 | * |
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[98e4ebf5] | 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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[03f2154e] | 9 | * http://www.OARcorp.com/rtems/license.html. |
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[c4808ca] | 10 | * |
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[c62d36f] | 11 | * $Id$ |
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| 12 | */ |
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| 13 | |
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| 14 | #include <rtems/system.h> |
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| 15 | #include <rtems/score/isr.h> |
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| 16 | |
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[9700578] | 17 | /* |
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| 18 | * This initializes the set of opcodes placed in each trap |
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| 19 | * table entry. The routine which installs a handler is responsible |
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| 20 | * for filling in the fields for the _handler address and the _vector |
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| 21 | * trap type. |
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| 22 | * |
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| 23 | * The constants following this structure are masks for the fields which |
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| 24 | * must be filled in when the handler is installed. |
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| 25 | */ |
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| 26 | |
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| 27 | const CPU_Trap_table_entry _CPU_Trap_slot_template = { |
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| 28 | 0xa1480000, /* mov %psr, %l0 */ |
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| 29 | 0x29000000, /* sethi %hi(_handler), %l4 */ |
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| 30 | 0x81c52000, /* jmp %l4 + %lo(_handler) */ |
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| 31 | 0xa6102000 /* mov _vector, %l3 */ |
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| 32 | }; |
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| 33 | |
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| 34 | /*PAGE |
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| 35 | * |
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| 36 | * _CPU_Initialize |
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[c62d36f] | 37 | * |
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| 38 | * This routine performs processor dependent initialization. |
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| 39 | * |
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[9700578] | 40 | * Input Parameters: |
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[c62d36f] | 41 | * cpu_table - CPU table to initialize |
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| 42 | * thread_dispatch - address of disptaching routine |
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[9700578] | 43 | * |
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| 44 | * Output Parameters: NONE |
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| 45 | * |
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| 46 | * NOTE: There is no need to save the pointer to the thread dispatch routine. |
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| 47 | * The SPARC's assembly code can reference it directly with no problems. |
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[c62d36f] | 48 | */ |
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| 49 | |
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| 50 | void _CPU_Initialize( |
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| 51 | rtems_cpu_table *cpu_table, |
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[9700578] | 52 | void (*thread_dispatch) /* ignored on this CPU */ |
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[c62d36f] | 53 | ) |
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| 54 | { |
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[9700578] | 55 | void *pointer; |
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[e1a06d1b] | 56 | |
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| 57 | #ifndef NO_TABLE_MOVE |
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[9700578] | 58 | unsigned32 trap_table_start; |
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| 59 | unsigned32 tbr_value; |
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| 60 | CPU_Trap_table_entry *old_tbr; |
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| 61 | CPU_Trap_table_entry *trap_table; |
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[c62d36f] | 62 | |
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| 63 | /* |
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[9700578] | 64 | * Install the executive's trap table. All entries from the original |
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| 65 | * trap table are copied into the executive's trap table. This is essential |
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| 66 | * since this preserves critical trap handlers such as the window underflow |
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| 67 | * and overflow handlers. It is the responsibility of the BSP to provide |
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| 68 | * install these in the initial trap table. |
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[c62d36f] | 69 | */ |
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[e1a06d1b] | 70 | |
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[9700578] | 71 | |
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| 72 | trap_table_start = (unsigned32) &_CPU_Trap_Table_area; |
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| 73 | if (trap_table_start & (SPARC_TRAP_TABLE_ALIGNMENT-1)) |
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| 74 | trap_table_start = (trap_table_start + SPARC_TRAP_TABLE_ALIGNMENT) & |
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| 75 | ~(SPARC_TRAP_TABLE_ALIGNMENT-1); |
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| 76 | |
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| 77 | trap_table = (CPU_Trap_table_entry *) trap_table_start; |
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| 78 | |
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| 79 | sparc_get_tbr( tbr_value ); |
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[c62d36f] | 80 | |
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[9700578] | 81 | old_tbr = (CPU_Trap_table_entry *) (tbr_value & 0xfffff000); |
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| 82 | |
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| 83 | memcpy( trap_table, (void *) old_tbr, 256 * sizeof( CPU_Trap_table_entry ) ); |
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| 84 | |
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| 85 | sparc_set_tbr( trap_table_start ); |
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[c62d36f] | 86 | |
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[e1a06d1b] | 87 | #endif |
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| 88 | |
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[c62d36f] | 89 | /* |
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[9700578] | 90 | * This seems to be the most appropriate way to obtain an initial |
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| 91 | * FP context on the SPARC. The NULL fp context is copied it to |
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| 92 | * the task's FP context during Context_Initialize. |
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[c62d36f] | 93 | */ |
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| 94 | |
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| 95 | pointer = &_CPU_Null_fp_context; |
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| 96 | _CPU_Context_save_fp( &pointer ); |
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| 97 | |
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[9700578] | 98 | /* |
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| 99 | * Grab our own copy of the user's CPU table. |
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| 100 | */ |
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| 101 | |
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[c62d36f] | 102 | _CPU_Table = *cpu_table; |
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| 103 | } |
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| 104 | |
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| 105 | /*PAGE |
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| 106 | * |
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| 107 | * _CPU_ISR_Get_level |
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[9700578] | 108 | * |
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| 109 | * Input Parameters: NONE |
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| 110 | * |
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| 111 | * Output Parameters: |
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| 112 | * returns the current interrupt level (PIL field of the PSR) |
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[c62d36f] | 113 | */ |
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| 114 | |
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| 115 | unsigned32 _CPU_ISR_Get_level( void ) |
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| 116 | { |
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| 117 | unsigned32 level; |
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| 118 | |
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| 119 | sparc_get_interrupt_level( level ); |
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| 120 | |
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| 121 | return level; |
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| 122 | } |
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| 123 | |
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[9700578] | 124 | /*PAGE |
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| 125 | * |
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| 126 | * _CPU_ISR_install_raw_handler |
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| 127 | * |
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| 128 | * This routine installs the specified handler as a "raw" non-executive |
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| 129 | * supported trap handler (a.k.a. interrupt service routine). |
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| 130 | * |
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| 131 | * Input Parameters: |
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| 132 | * vector - trap table entry number plus synchronous |
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| 133 | * vs. asynchronous information |
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| 134 | * new_handler - address of the handler to be installed |
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| 135 | * old_handler - pointer to an address of the handler previously installed |
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| 136 | * |
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| 137 | * Output Parameters: NONE |
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| 138 | * *new_handler - address of the handler previously installed |
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| 139 | * |
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| 140 | * NOTE: |
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| 141 | * |
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| 142 | * On the SPARC, there are really only 256 vectors. However, the executive |
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| 143 | * has no easy, fast, reliable way to determine which traps are synchronous |
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| 144 | * and which are asynchronous. By default, synchronous traps return to the |
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| 145 | * instruction which caused the interrupt. So if you install a software |
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| 146 | * trap handler as an executive interrupt handler (which is desirable since |
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| 147 | * RTEMS takes care of window and register issues), then the executive needs |
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| 148 | * to know that the return address is to the trap rather than the instruction |
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| 149 | * following the trap. |
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| 150 | * |
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| 151 | * So vectors 0 through 255 are treated as regular asynchronous traps which |
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| 152 | * provide the "correct" return address. Vectors 256 through 512 are assumed |
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| 153 | * by the executive to be synchronous and to require that the return address |
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| 154 | * be fudged. |
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| 155 | * |
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| 156 | * If you use this mechanism to install a trap handler which must reexecute |
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| 157 | * the instruction which caused the trap, then it should be installed as |
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| 158 | * an asynchronous trap. This will avoid the executive changing the return |
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| 159 | * address. |
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| 160 | */ |
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| 161 | |
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| 162 | void _CPU_ISR_install_raw_handler( |
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| 163 | unsigned32 vector, |
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| 164 | proc_ptr new_handler, |
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| 165 | proc_ptr *old_handler |
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| 166 | ) |
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| 167 | { |
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| 168 | unsigned32 real_vector; |
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| 169 | CPU_Trap_table_entry *tbr; |
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| 170 | CPU_Trap_table_entry *slot; |
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| 171 | unsigned32 u32_tbr; |
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| 172 | unsigned32 u32_handler; |
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| 173 | |
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| 174 | /* |
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| 175 | * Get the "real" trap number for this vector ignoring the synchronous |
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| 176 | * versus asynchronous indicator included with our vector numbers. |
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| 177 | */ |
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| 178 | |
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| 179 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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| 180 | |
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| 181 | /* |
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| 182 | * Get the current base address of the trap table and calculate a pointer |
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| 183 | * to the slot we are interested in. |
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| 184 | */ |
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| 185 | |
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| 186 | sparc_get_tbr( u32_tbr ); |
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| 187 | |
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| 188 | u32_tbr &= 0xfffff000; |
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| 189 | |
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| 190 | tbr = (CPU_Trap_table_entry *) u32_tbr; |
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| 191 | |
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| 192 | slot = &tbr[ real_vector ]; |
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| 193 | |
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| 194 | /* |
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| 195 | * Get the address of the old_handler from the trap table. |
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| 196 | * |
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| 197 | * NOTE: The old_handler returned will be bogus if it does not follow |
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| 198 | * the RTEMS model. |
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| 199 | */ |
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| 200 | |
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| 201 | #define HIGH_BITS_MASK 0xFFFFFC00 |
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| 202 | #define HIGH_BITS_SHIFT 10 |
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| 203 | #define LOW_BITS_MASK 0x000003FF |
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| 204 | |
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| 205 | if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) { |
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| 206 | u32_handler = |
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| 207 | ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) | |
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| 208 | (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK); |
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| 209 | *old_handler = (proc_ptr) u32_handler; |
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| 210 | } else |
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| 211 | *old_handler = 0; |
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| 212 | |
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| 213 | /* |
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| 214 | * Copy the template to the slot and then fix it. |
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| 215 | */ |
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| 216 | |
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| 217 | *slot = _CPU_Trap_slot_template; |
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| 218 | |
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| 219 | u32_handler = (unsigned32) new_handler; |
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| 220 | |
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| 221 | slot->mov_vector_l3 |= vector; |
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| 222 | slot->sethi_of_handler_to_l4 |= |
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| 223 | (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT; |
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| 224 | slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK); |
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| 225 | } |
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| 226 | |
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| 227 | /*PAGE |
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| 228 | * |
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| 229 | * _CPU_ISR_install_vector |
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[c62d36f] | 230 | * |
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| 231 | * This kernel routine installs the RTEMS handler for the |
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| 232 | * specified vector. |
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| 233 | * |
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| 234 | * Input parameters: |
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[9700578] | 235 | * vector - interrupt vector number |
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| 236 | * new_handler - replacement ISR for this vector number |
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| 237 | * old_handler - pointer to former ISR for this vector number |
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[c62d36f] | 238 | * |
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[9700578] | 239 | * Output parameters: |
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| 240 | * *old_handler - former ISR for this vector number |
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[c62d36f] | 241 | * |
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| 242 | */ |
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| 243 | |
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| 244 | void _CPU_ISR_install_vector( |
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| 245 | unsigned32 vector, |
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| 246 | proc_ptr new_handler, |
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| 247 | proc_ptr *old_handler |
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| 248 | ) |
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| 249 | { |
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[9700578] | 250 | unsigned32 real_vector; |
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| 251 | proc_ptr ignored; |
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| 252 | |
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| 253 | /* |
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| 254 | * Get the "real" trap number for this vector ignoring the synchronous |
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| 255 | * versus asynchronous indicator included with our vector numbers. |
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| 256 | */ |
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| 257 | |
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| 258 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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[c62d36f] | 259 | |
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| 260 | /* |
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[9700578] | 261 | * Return the previous ISR handler. |
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[c62d36f] | 262 | */ |
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| 263 | |
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[9700578] | 264 | *old_handler = _ISR_Vector_table[ real_vector ]; |
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| 265 | |
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[c62d36f] | 266 | /* |
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[9700578] | 267 | * Install the wrapper so this ISR can be invoked properly. |
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[c62d36f] | 268 | */ |
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| 269 | |
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[9700578] | 270 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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[c62d36f] | 271 | |
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[9700578] | 272 | /* |
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| 273 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 274 | * be used by the _ISR_Handler so the user gets control. |
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| 275 | */ |
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[c62d36f] | 276 | |
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[9700578] | 277 | _ISR_Vector_table[ real_vector ] = new_handler; |
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[c62d36f] | 278 | } |
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| 279 | |
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| 280 | /*PAGE |
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| 281 | * |
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| 282 | * _CPU_Context_Initialize |
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[9700578] | 283 | * |
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| 284 | * This kernel routine initializes the basic non-FP context area associated |
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| 285 | * with each thread. |
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| 286 | * |
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| 287 | * Input parameters: |
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| 288 | * the_context - pointer to the context area |
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| 289 | * stack_base - address of memory for the SPARC |
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| 290 | * size - size in bytes of the stack area |
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| 291 | * new_level - interrupt level for this context area |
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| 292 | * entry_point - the starting execution point for this this context |
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| 293 | * is_fp - TRUE if this context is associated with an FP thread |
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| 294 | * |
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| 295 | * Output parameters: NONE |
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[c62d36f] | 296 | */ |
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| 297 | |
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| 298 | void _CPU_Context_Initialize( |
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[9700578] | 299 | Context_Control *the_context, |
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| 300 | unsigned32 *stack_base, |
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| 301 | unsigned32 size, |
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| 302 | unsigned32 new_level, |
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| 303 | void *entry_point, |
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| 304 | boolean is_fp |
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[c62d36f] | 305 | ) |
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| 306 | { |
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[9700578] | 307 | unsigned32 stack_high; /* highest "stack aligned" address */ |
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| 308 | unsigned32 the_size; |
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[c62d36f] | 309 | unsigned32 tmp_psr; |
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| 310 | |
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| 311 | /* |
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| 312 | * On CPUs with stacks which grow down (i.e. SPARC), we build the stack |
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[9700578] | 313 | * based on the stack_high address. |
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[c62d36f] | 314 | */ |
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| 315 | |
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[9700578] | 316 | stack_high = ((unsigned32)(stack_base) + size); |
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| 317 | stack_high &= ~(CPU_STACK_ALIGNMENT - 1); |
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[c62d36f] | 318 | |
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[9700578] | 319 | the_size = size & ~(CPU_STACK_ALIGNMENT - 1); |
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[c62d36f] | 320 | |
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| 321 | /* |
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[9700578] | 322 | * See the README in this directory for a diagram of the stack. |
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[c62d36f] | 323 | */ |
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| 324 | |
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[9700578] | 325 | the_context->o7 = ((unsigned32) entry_point) - 8; |
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| 326 | the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE; |
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| 327 | the_context->i6_fp = stack_high; |
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[c62d36f] | 328 | |
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[9700578] | 329 | /* |
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| 330 | * Build the PSR for the task. Most everything can be 0 and the |
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| 331 | * CWP is corrected during the context switch. |
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| 332 | * |
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| 333 | * The EF bit determines if the floating point unit is available. |
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| 334 | * The FPU is ONLY enabled if the context is associated with an FP task |
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| 335 | * and this SPARC model has an FPU. |
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| 336 | */ |
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[c62d36f] | 337 | |
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| 338 | sparc_get_psr( tmp_psr ); |
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[9700578] | 339 | tmp_psr &= ~SPARC_PSR_PIL_MASK; |
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| 340 | tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK; |
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| 341 | tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */ |
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| 342 | |
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| 343 | #if (SPARC_HAS_FPU == 1) |
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| 344 | /* |
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| 345 | * If this bit is not set, then a task gets a fault when it accesses |
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| 346 | * a floating point register. This is a nice way to detect floating |
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| 347 | * point tasks which are not currently declared as such. |
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| 348 | */ |
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| 349 | |
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| 350 | if ( is_fp ) |
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| 351 | tmp_psr |= SPARC_PSR_EF_MASK; |
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| 352 | #endif |
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| 353 | the_context->psr = tmp_psr; |
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[c62d36f] | 354 | } |
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