[c62d36f] | 1 | /* |
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| 2 | * SPARC Dependent Source |
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| 3 | * |
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[08311cc3] | 4 | * COPYRIGHT (c) 1989-1999. |
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[c4808ca] | 5 | * On-Line Applications Research Corporation (OAR). |
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| 6 | * |
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[98e4ebf5] | 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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[85ab70f] | 9 | * http://www.rtems.com/license/LICENSE. |
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[c4808ca] | 10 | * |
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[c62d36f] | 11 | * $Id$ |
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| 12 | */ |
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| 13 | |
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| 14 | #include <rtems/system.h> |
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| 15 | #include <rtems/score/isr.h> |
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[5996c48] | 16 | #include <rtems/rtems/cache.h> |
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[c62d36f] | 17 | |
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[9700578] | 18 | /* |
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| 19 | * This initializes the set of opcodes placed in each trap |
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| 20 | * table entry. The routine which installs a handler is responsible |
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| 21 | * for filling in the fields for the _handler address and the _vector |
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| 22 | * trap type. |
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| 23 | * |
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| 24 | * The constants following this structure are masks for the fields which |
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| 25 | * must be filled in when the handler is installed. |
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| 26 | */ |
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| 27 | |
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| 28 | const CPU_Trap_table_entry _CPU_Trap_slot_template = { |
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| 29 | 0xa1480000, /* mov %psr, %l0 */ |
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| 30 | 0x29000000, /* sethi %hi(_handler), %l4 */ |
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| 31 | 0x81c52000, /* jmp %l4 + %lo(_handler) */ |
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| 32 | 0xa6102000 /* mov _vector, %l3 */ |
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| 33 | }; |
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| 34 | |
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| 35 | /*PAGE |
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| 36 | * |
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| 37 | * _CPU_Initialize |
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[c62d36f] | 38 | * |
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| 39 | * This routine performs processor dependent initialization. |
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| 40 | * |
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[9700578] | 41 | * Input Parameters: |
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[c62d36f] | 42 | * cpu_table - CPU table to initialize |
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| 43 | * thread_dispatch - address of disptaching routine |
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[9700578] | 44 | * |
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| 45 | * Output Parameters: NONE |
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| 46 | * |
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| 47 | * NOTE: There is no need to save the pointer to the thread dispatch routine. |
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| 48 | * The SPARC's assembly code can reference it directly with no problems. |
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[c62d36f] | 49 | */ |
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| 50 | |
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| 51 | void _CPU_Initialize( |
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| 52 | rtems_cpu_table *cpu_table, |
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[9700578] | 53 | void (*thread_dispatch) /* ignored on this CPU */ |
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[c62d36f] | 54 | ) |
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| 55 | { |
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[477e2d19] | 56 | #if (SPARC_HAS_FPU == 1) |
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[a19dd35] | 57 | void *pointer; |
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[477e2d19] | 58 | |
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[c62d36f] | 59 | /* |
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[9700578] | 60 | * This seems to be the most appropriate way to obtain an initial |
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| 61 | * FP context on the SPARC. The NULL fp context is copied it to |
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| 62 | * the task's FP context during Context_Initialize. |
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[c62d36f] | 63 | */ |
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| 64 | |
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| 65 | pointer = &_CPU_Null_fp_context; |
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| 66 | _CPU_Context_save_fp( &pointer ); |
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[477e2d19] | 67 | #endif |
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[c62d36f] | 68 | |
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[9700578] | 69 | /* |
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| 70 | * Grab our own copy of the user's CPU table. |
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| 71 | */ |
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| 72 | |
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[c62d36f] | 73 | _CPU_Table = *cpu_table; |
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| 74 | } |
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| 75 | |
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| 76 | /*PAGE |
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| 77 | * |
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| 78 | * _CPU_ISR_Get_level |
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[9700578] | 79 | * |
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| 80 | * Input Parameters: NONE |
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| 81 | * |
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| 82 | * Output Parameters: |
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| 83 | * returns the current interrupt level (PIL field of the PSR) |
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[c62d36f] | 84 | */ |
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| 85 | |
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[2a0a6851] | 86 | uint32_t _CPU_ISR_Get_level( void ) |
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[c62d36f] | 87 | { |
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[2a0a6851] | 88 | uint32_t level; |
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[c62d36f] | 89 | |
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| 90 | sparc_get_interrupt_level( level ); |
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| 91 | |
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| 92 | return level; |
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| 93 | } |
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| 94 | |
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[9700578] | 95 | /*PAGE |
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| 96 | * |
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| 97 | * _CPU_ISR_install_raw_handler |
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| 98 | * |
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| 99 | * This routine installs the specified handler as a "raw" non-executive |
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| 100 | * supported trap handler (a.k.a. interrupt service routine). |
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| 101 | * |
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| 102 | * Input Parameters: |
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| 103 | * vector - trap table entry number plus synchronous |
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| 104 | * vs. asynchronous information |
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| 105 | * new_handler - address of the handler to be installed |
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| 106 | * old_handler - pointer to an address of the handler previously installed |
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| 107 | * |
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| 108 | * Output Parameters: NONE |
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| 109 | * *new_handler - address of the handler previously installed |
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| 110 | * |
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| 111 | * NOTE: |
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| 112 | * |
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| 113 | * On the SPARC, there are really only 256 vectors. However, the executive |
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| 114 | * has no easy, fast, reliable way to determine which traps are synchronous |
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| 115 | * and which are asynchronous. By default, synchronous traps return to the |
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| 116 | * instruction which caused the interrupt. So if you install a software |
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| 117 | * trap handler as an executive interrupt handler (which is desirable since |
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| 118 | * RTEMS takes care of window and register issues), then the executive needs |
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| 119 | * to know that the return address is to the trap rather than the instruction |
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| 120 | * following the trap. |
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| 121 | * |
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| 122 | * So vectors 0 through 255 are treated as regular asynchronous traps which |
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| 123 | * provide the "correct" return address. Vectors 256 through 512 are assumed |
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| 124 | * by the executive to be synchronous and to require that the return address |
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| 125 | * be fudged. |
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| 126 | * |
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| 127 | * If you use this mechanism to install a trap handler which must reexecute |
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| 128 | * the instruction which caused the trap, then it should be installed as |
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| 129 | * an asynchronous trap. This will avoid the executive changing the return |
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| 130 | * address. |
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| 131 | */ |
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| 132 | |
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| 133 | void _CPU_ISR_install_raw_handler( |
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[2a0a6851] | 134 | uint32_t vector, |
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[9700578] | 135 | proc_ptr new_handler, |
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| 136 | proc_ptr *old_handler |
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| 137 | ) |
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| 138 | { |
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[2a0a6851] | 139 | uint32_t real_vector; |
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[9700578] | 140 | CPU_Trap_table_entry *tbr; |
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| 141 | CPU_Trap_table_entry *slot; |
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[2a0a6851] | 142 | uint32_t u32_tbr; |
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| 143 | uint32_t u32_handler; |
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[9700578] | 144 | |
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| 145 | /* |
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| 146 | * Get the "real" trap number for this vector ignoring the synchronous |
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| 147 | * versus asynchronous indicator included with our vector numbers. |
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| 148 | */ |
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| 149 | |
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| 150 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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| 151 | |
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| 152 | /* |
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| 153 | * Get the current base address of the trap table and calculate a pointer |
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| 154 | * to the slot we are interested in. |
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| 155 | */ |
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| 156 | |
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| 157 | sparc_get_tbr( u32_tbr ); |
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| 158 | |
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| 159 | u32_tbr &= 0xfffff000; |
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| 160 | |
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| 161 | tbr = (CPU_Trap_table_entry *) u32_tbr; |
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| 162 | |
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| 163 | slot = &tbr[ real_vector ]; |
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| 164 | |
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| 165 | /* |
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| 166 | * Get the address of the old_handler from the trap table. |
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| 167 | * |
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| 168 | * NOTE: The old_handler returned will be bogus if it does not follow |
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| 169 | * the RTEMS model. |
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| 170 | */ |
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| 171 | |
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| 172 | #define HIGH_BITS_MASK 0xFFFFFC00 |
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| 173 | #define HIGH_BITS_SHIFT 10 |
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| 174 | #define LOW_BITS_MASK 0x000003FF |
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| 175 | |
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| 176 | if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) { |
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| 177 | u32_handler = |
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| 178 | ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) | |
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| 179 | (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK); |
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| 180 | *old_handler = (proc_ptr) u32_handler; |
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| 181 | } else |
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| 182 | *old_handler = 0; |
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| 183 | |
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| 184 | /* |
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| 185 | * Copy the template to the slot and then fix it. |
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| 186 | */ |
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| 187 | |
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| 188 | *slot = _CPU_Trap_slot_template; |
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| 189 | |
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[2a0a6851] | 190 | u32_handler = (uint32_t ) new_handler; |
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[9700578] | 191 | |
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| 192 | slot->mov_vector_l3 |= vector; |
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| 193 | slot->sethi_of_handler_to_l4 |= |
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| 194 | (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT; |
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| 195 | slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK); |
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[477e2d19] | 196 | |
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| 197 | /* need to flush icache after this !!! */ |
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| 198 | |
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| 199 | rtems_cache_invalidate_entire_instruction(); |
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| 200 | |
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[9700578] | 201 | } |
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| 202 | |
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| 203 | /*PAGE |
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| 204 | * |
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| 205 | * _CPU_ISR_install_vector |
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[c62d36f] | 206 | * |
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| 207 | * This kernel routine installs the RTEMS handler for the |
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| 208 | * specified vector. |
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| 209 | * |
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| 210 | * Input parameters: |
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[9700578] | 211 | * vector - interrupt vector number |
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| 212 | * new_handler - replacement ISR for this vector number |
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| 213 | * old_handler - pointer to former ISR for this vector number |
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[c62d36f] | 214 | * |
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[9700578] | 215 | * Output parameters: |
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| 216 | * *old_handler - former ISR for this vector number |
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[c62d36f] | 217 | * |
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| 218 | */ |
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| 219 | |
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| 220 | void _CPU_ISR_install_vector( |
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[2a0a6851] | 221 | uint32_t vector, |
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[c62d36f] | 222 | proc_ptr new_handler, |
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| 223 | proc_ptr *old_handler |
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| 224 | ) |
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| 225 | { |
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[2a0a6851] | 226 | uint32_t real_vector; |
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[9700578] | 227 | proc_ptr ignored; |
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| 228 | |
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| 229 | /* |
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| 230 | * Get the "real" trap number for this vector ignoring the synchronous |
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| 231 | * versus asynchronous indicator included with our vector numbers. |
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| 232 | */ |
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| 233 | |
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| 234 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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[c62d36f] | 235 | |
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| 236 | /* |
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[9700578] | 237 | * Return the previous ISR handler. |
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[c62d36f] | 238 | */ |
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| 239 | |
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[9700578] | 240 | *old_handler = _ISR_Vector_table[ real_vector ]; |
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| 241 | |
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[c62d36f] | 242 | /* |
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[9700578] | 243 | * Install the wrapper so this ISR can be invoked properly. |
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[c62d36f] | 244 | */ |
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| 245 | |
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[9700578] | 246 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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[c62d36f] | 247 | |
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[9700578] | 248 | /* |
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| 249 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 250 | * be used by the _ISR_Handler so the user gets control. |
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| 251 | */ |
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[c62d36f] | 252 | |
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[9700578] | 253 | _ISR_Vector_table[ real_vector ] = new_handler; |
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[c62d36f] | 254 | } |
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| 255 | |
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| 256 | /*PAGE |
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| 257 | * |
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| 258 | * _CPU_Context_Initialize |
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[9700578] | 259 | * |
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| 260 | * This kernel routine initializes the basic non-FP context area associated |
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| 261 | * with each thread. |
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| 262 | * |
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| 263 | * Input parameters: |
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| 264 | * the_context - pointer to the context area |
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| 265 | * stack_base - address of memory for the SPARC |
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| 266 | * size - size in bytes of the stack area |
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| 267 | * new_level - interrupt level for this context area |
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| 268 | * entry_point - the starting execution point for this this context |
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| 269 | * is_fp - TRUE if this context is associated with an FP thread |
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| 270 | * |
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| 271 | * Output parameters: NONE |
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[c62d36f] | 272 | */ |
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| 273 | |
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| 274 | void _CPU_Context_Initialize( |
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[9700578] | 275 | Context_Control *the_context, |
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[2a0a6851] | 276 | uint32_t *stack_base, |
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| 277 | uint32_t size, |
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| 278 | uint32_t new_level, |
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[9700578] | 279 | void *entry_point, |
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| 280 | boolean is_fp |
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[c62d36f] | 281 | ) |
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| 282 | { |
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[2a0a6851] | 283 | uint32_t stack_high; /* highest "stack aligned" address */ |
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| 284 | uint32_t the_size; |
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| 285 | uint32_t tmp_psr; |
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[c62d36f] | 286 | |
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| 287 | /* |
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| 288 | * On CPUs with stacks which grow down (i.e. SPARC), we build the stack |
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[9700578] | 289 | * based on the stack_high address. |
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[c62d36f] | 290 | */ |
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| 291 | |
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[2a0a6851] | 292 | stack_high = ((uint32_t )(stack_base) + size); |
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[9700578] | 293 | stack_high &= ~(CPU_STACK_ALIGNMENT - 1); |
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[c62d36f] | 294 | |
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[9700578] | 295 | the_size = size & ~(CPU_STACK_ALIGNMENT - 1); |
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[c62d36f] | 296 | |
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| 297 | /* |
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[9700578] | 298 | * See the README in this directory for a diagram of the stack. |
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[c62d36f] | 299 | */ |
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| 300 | |
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[2a0a6851] | 301 | the_context->o7 = ((uint32_t ) entry_point) - 8; |
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[9700578] | 302 | the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE; |
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| 303 | the_context->i6_fp = stack_high; |
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[c62d36f] | 304 | |
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[9700578] | 305 | /* |
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| 306 | * Build the PSR for the task. Most everything can be 0 and the |
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| 307 | * CWP is corrected during the context switch. |
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| 308 | * |
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| 309 | * The EF bit determines if the floating point unit is available. |
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| 310 | * The FPU is ONLY enabled if the context is associated with an FP task |
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| 311 | * and this SPARC model has an FPU. |
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| 312 | */ |
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[c62d36f] | 313 | |
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| 314 | sparc_get_psr( tmp_psr ); |
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[9700578] | 315 | tmp_psr &= ~SPARC_PSR_PIL_MASK; |
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| 316 | tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK; |
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| 317 | tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */ |
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| 318 | |
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| 319 | #if (SPARC_HAS_FPU == 1) |
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| 320 | /* |
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| 321 | * If this bit is not set, then a task gets a fault when it accesses |
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| 322 | * a floating point register. This is a nice way to detect floating |
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| 323 | * point tasks which are not currently declared as such. |
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| 324 | */ |
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| 325 | |
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| 326 | if ( is_fp ) |
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| 327 | tmp_psr |= SPARC_PSR_EF_MASK; |
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| 328 | #endif |
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| 329 | the_context->psr = tmp_psr; |
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[c62d36f] | 330 | } |
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