[e0f91da] | 1 | /** |
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| 2 | * @file |
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[c62d36f] | 3 | * |
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[e0f91da] | 4 | * @brief SPARC CPU Dependent Source |
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| 5 | */ |
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| 6 | |
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| 7 | /* |
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[48816d7] | 8 | * COPYRIGHT (c) 1989-2007. |
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[c4808ca] | 9 | * On-Line Applications Research Corporation (OAR). |
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| 10 | * |
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[146adb1] | 11 | * Copyright (c) 2017 embedded brains GmbH |
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| 12 | * |
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[98e4ebf5] | 13 | * The license and distribution terms for this file may be |
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| 14 | * found in the file LICENSE in this distribution or at |
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[c499856] | 15 | * http://www.rtems.org/license/LICENSE. |
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[c62d36f] | 16 | */ |
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| 17 | |
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[febaa8a] | 18 | #ifdef HAVE_CONFIG_H |
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| 19 | #include "config.h" |
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| 20 | #endif |
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| 21 | |
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[c62d36f] | 22 | #include <rtems/system.h> |
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| 23 | #include <rtems/score/isr.h> |
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[f8ad6c6f] | 24 | #include <rtems/score/percpu.h> |
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[022851a] | 25 | #include <rtems/score/tls.h> |
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[146adb1] | 26 | #include <rtems/score/thread.h> |
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[5996c48] | 27 | #include <rtems/rtems/cache.h> |
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[c62d36f] | 28 | |
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[2764bd43] | 29 | #if SPARC_HAS_FPU == 1 |
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| 30 | RTEMS_STATIC_ASSERT( |
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| 31 | offsetof( Per_CPU_Control, cpu_per_cpu.fsr) |
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| 32 | == SPARC_PER_CPU_FSR_OFFSET, |
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| 33 | SPARC_PER_CPU_FSR_OFFSET |
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| 34 | ); |
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[146adb1] | 35 | |
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| 36 | #if defined(SPARC_USE_LAZY_FP_SWITCH) |
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| 37 | RTEMS_STATIC_ASSERT( |
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| 38 | offsetof( Per_CPU_Control, cpu_per_cpu.fp_owner) |
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| 39 | == SPARC_PER_CPU_FP_OWNER_OFFSET, |
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| 40 | SPARC_PER_CPU_FP_OWNER_OFFSET |
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| 41 | ); |
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| 42 | #endif |
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[2764bd43] | 43 | #endif |
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| 44 | |
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[97cf623d] | 45 | #define SPARC_ASSERT_OFFSET(field, off) \ |
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| 46 | RTEMS_STATIC_ASSERT( \ |
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| 47 | offsetof(Context_Control, field) == off ## _OFFSET, \ |
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| 48 | Context_Control_offset_ ## field \ |
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| 49 | ) |
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| 50 | |
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| 51 | SPARC_ASSERT_OFFSET(g5, G5); |
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| 52 | SPARC_ASSERT_OFFSET(g7, G7); |
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[b2ec2d15] | 53 | |
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| 54 | RTEMS_STATIC_ASSERT( |
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| 55 | offsetof(Context_Control, l0_and_l1) == L0_OFFSET, |
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| 56 | Context_Control_offset_L0 |
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| 57 | ); |
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| 58 | |
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| 59 | RTEMS_STATIC_ASSERT( |
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| 60 | offsetof(Context_Control, l0_and_l1) + 4 == L1_OFFSET, |
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| 61 | Context_Control_offset_L1 |
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| 62 | ); |
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| 63 | |
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[97cf623d] | 64 | SPARC_ASSERT_OFFSET(l2, L2); |
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| 65 | SPARC_ASSERT_OFFSET(l3, L3); |
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| 66 | SPARC_ASSERT_OFFSET(l4, L4); |
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| 67 | SPARC_ASSERT_OFFSET(l5, L5); |
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| 68 | SPARC_ASSERT_OFFSET(l6, L6); |
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| 69 | SPARC_ASSERT_OFFSET(l7, L7); |
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| 70 | SPARC_ASSERT_OFFSET(i0, I0); |
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| 71 | SPARC_ASSERT_OFFSET(i1, I1); |
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| 72 | SPARC_ASSERT_OFFSET(i2, I2); |
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| 73 | SPARC_ASSERT_OFFSET(i3, I3); |
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| 74 | SPARC_ASSERT_OFFSET(i4, I4); |
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| 75 | SPARC_ASSERT_OFFSET(i5, I5); |
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| 76 | SPARC_ASSERT_OFFSET(i6_fp, I6_FP); |
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| 77 | SPARC_ASSERT_OFFSET(i7, I7); |
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| 78 | SPARC_ASSERT_OFFSET(o6_sp, O6_SP); |
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| 79 | SPARC_ASSERT_OFFSET(o7, O7); |
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| 80 | SPARC_ASSERT_OFFSET(psr, PSR); |
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| 81 | SPARC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE_STACK); |
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| 82 | |
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[38b59a6] | 83 | #if defined(RTEMS_SMP) |
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| 84 | SPARC_ASSERT_OFFSET(is_executing, SPARC_CONTEXT_CONTROL_IS_EXECUTING); |
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| 85 | #endif |
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| 86 | |
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[fedc6828] | 87 | #define SPARC_ASSERT_ISF_OFFSET(field, off) \ |
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| 88 | RTEMS_STATIC_ASSERT( \ |
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| 89 | offsetof(CPU_Interrupt_frame, field) == ISF_ ## off ## _OFFSET, \ |
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| 90 | CPU_Interrupt_frame_offset_ ## field \ |
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| 91 | ) |
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| 92 | |
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| 93 | SPARC_ASSERT_ISF_OFFSET(psr, PSR); |
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| 94 | SPARC_ASSERT_ISF_OFFSET(pc, PC); |
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| 95 | SPARC_ASSERT_ISF_OFFSET(npc, NPC); |
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| 96 | SPARC_ASSERT_ISF_OFFSET(g1, G1); |
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| 97 | SPARC_ASSERT_ISF_OFFSET(g2, G2); |
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| 98 | SPARC_ASSERT_ISF_OFFSET(g3, G3); |
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| 99 | SPARC_ASSERT_ISF_OFFSET(g4, G4); |
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| 100 | SPARC_ASSERT_ISF_OFFSET(g5, G5); |
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| 101 | SPARC_ASSERT_ISF_OFFSET(g7, G7); |
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| 102 | SPARC_ASSERT_ISF_OFFSET(i0, I0); |
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| 103 | SPARC_ASSERT_ISF_OFFSET(i1, I1); |
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| 104 | SPARC_ASSERT_ISF_OFFSET(i2, I2); |
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| 105 | SPARC_ASSERT_ISF_OFFSET(i3, I3); |
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| 106 | SPARC_ASSERT_ISF_OFFSET(i4, I4); |
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| 107 | SPARC_ASSERT_ISF_OFFSET(i5, I5); |
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| 108 | SPARC_ASSERT_ISF_OFFSET(i6_fp, I6_FP); |
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| 109 | SPARC_ASSERT_ISF_OFFSET(i7, I7); |
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| 110 | SPARC_ASSERT_ISF_OFFSET(y, Y); |
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| 111 | SPARC_ASSERT_ISF_OFFSET(tpc, TPC); |
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| 112 | |
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[146adb1] | 113 | #define SPARC_ASSERT_FP_OFFSET(field, off) \ |
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| 114 | RTEMS_STATIC_ASSERT( \ |
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| 115 | offsetof(Context_Control_fp, field) == SPARC_FP_CONTEXT_OFFSET_ ## off, \ |
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| 116 | Context_Control_fp_offset_ ## field \ |
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| 117 | ) |
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| 118 | |
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| 119 | SPARC_ASSERT_FP_OFFSET(f0_f1, F0_F1); |
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| 120 | SPARC_ASSERT_FP_OFFSET(f2_f3, F2_F3); |
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| 121 | SPARC_ASSERT_FP_OFFSET(f4_f5, F4_F5); |
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| 122 | SPARC_ASSERT_FP_OFFSET(f6_f7, F6_F7); |
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| 123 | SPARC_ASSERT_FP_OFFSET(f8_f9, F8_F9); |
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| 124 | SPARC_ASSERT_FP_OFFSET(f10_f11, F10_F11); |
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| 125 | SPARC_ASSERT_FP_OFFSET(f12_f13, F12_F13); |
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| 126 | SPARC_ASSERT_FP_OFFSET(f14_f15, F14_F15); |
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| 127 | SPARC_ASSERT_FP_OFFSET(f16_f17, F16_F17); |
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| 128 | SPARC_ASSERT_FP_OFFSET(f18_f19, F18_F19); |
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| 129 | SPARC_ASSERT_FP_OFFSET(f20_f21, F20_F21); |
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| 130 | SPARC_ASSERT_FP_OFFSET(f22_f23, F22_F23); |
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| 131 | SPARC_ASSERT_FP_OFFSET(f24_f25, F24_F25); |
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| 132 | SPARC_ASSERT_FP_OFFSET(f26_f27, F26_F27); |
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| 133 | SPARC_ASSERT_FP_OFFSET(f28_f29, F28_F29); |
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| 134 | SPARC_ASSERT_FP_OFFSET(f30_f31, F30_F31); |
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| 135 | SPARC_ASSERT_FP_OFFSET(fsr, FSR); |
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| 136 | |
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[76030c7] | 137 | RTEMS_STATIC_ASSERT( |
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[c539a865] | 138 | sizeof(SPARC_Minimum_stack_frame) == SPARC_MINIMUM_STACK_FRAME_SIZE, |
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| 139 | SPARC_MINIMUM_STACK_FRAME_SIZE |
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| 140 | ); |
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| 141 | |
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[fedc6828] | 142 | /* https://devel.rtems.org/ticket/2352 */ |
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| 143 | RTEMS_STATIC_ASSERT( |
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| 144 | sizeof(CPU_Interrupt_frame) % CPU_ALIGNMENT == 0, |
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| 145 | CPU_Interrupt_frame_alignment |
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| 146 | ); |
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| 147 | |
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[28b4c7ac] | 148 | /* |
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| 149 | * This initializes the set of opcodes placed in each trap |
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| 150 | * table entry. The routine which installs a handler is responsible |
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| 151 | * for filling in the fields for the _handler address and the _vector |
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| 152 | * trap type. |
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| 153 | * |
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| 154 | * The constants following this structure are masks for the fields which |
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| 155 | * must be filled in when the handler is installed. |
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| 156 | */ |
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| 157 | const CPU_Trap_table_entry _CPU_Trap_slot_template = { |
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| 158 | 0xa1480000, /* mov %psr, %l0 */ |
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| 159 | 0x29000000, /* sethi %hi(_handler), %l4 */ |
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| 160 | 0x81c52000, /* jmp %l4 + %lo(_handler) */ |
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| 161 | 0xa6102000 /* mov _vector, %l3 */ |
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| 162 | }; |
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| 163 | |
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[7c2f2448] | 164 | /* |
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[9700578] | 165 | * _CPU_Initialize |
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[c62d36f] | 166 | * |
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| 167 | * This routine performs processor dependent initialization. |
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| 168 | * |
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[c03e2bc] | 169 | * INPUT PARAMETERS: NONE |
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[9700578] | 170 | * |
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| 171 | * Output Parameters: NONE |
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[80f7732] | 172 | * |
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[9700578] | 173 | * NOTE: There is no need to save the pointer to the thread dispatch routine. |
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| 174 | * The SPARC's assembly code can reference it directly with no problems. |
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[c62d36f] | 175 | */ |
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| 176 | |
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[c03e2bc] | 177 | void _CPU_Initialize(void) |
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[c62d36f] | 178 | { |
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[146adb1] | 179 | #if defined(SPARC_USE_LAZY_FP_SWITCH) |
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| 180 | __asm__ volatile ( |
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| 181 | ".global SPARC_THREAD_CONTROL_REGISTERS_FP_CONTEXT_OFFSET\n" |
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| 182 | ".set SPARC_THREAD_CONTROL_REGISTERS_FP_CONTEXT_OFFSET, %0\n" |
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| 183 | ".global SPARC_THREAD_CONTROL_FP_CONTEXT_OFFSET\n" |
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| 184 | ".set SPARC_THREAD_CONTROL_FP_CONTEXT_OFFSET, %1\n" |
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| 185 | : |
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| 186 | : "i" (offsetof(Thread_Control, Registers.fp_context)), |
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| 187 | "i" (offsetof(Thread_Control, fp_context)) |
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| 188 | ); |
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[477e2d19] | 189 | #endif |
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[c62d36f] | 190 | } |
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| 191 | |
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[2a0a6851] | 192 | uint32_t _CPU_ISR_Get_level( void ) |
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[c62d36f] | 193 | { |
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[2a0a6851] | 194 | uint32_t level; |
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[80f7732] | 195 | |
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[c62d36f] | 196 | sparc_get_interrupt_level( level ); |
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[80f7732] | 197 | |
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[c62d36f] | 198 | return level; |
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| 199 | } |
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| 200 | |
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[7c2f2448] | 201 | /* |
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[9700578] | 202 | * _CPU_ISR_install_raw_handler |
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| 203 | * |
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| 204 | * This routine installs the specified handler as a "raw" non-executive |
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| 205 | * supported trap handler (a.k.a. interrupt service routine). |
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| 206 | * |
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| 207 | * Input Parameters: |
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[80f7732] | 208 | * vector - trap table entry number plus synchronous |
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[9700578] | 209 | * vs. asynchronous information |
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| 210 | * new_handler - address of the handler to be installed |
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| 211 | * old_handler - pointer to an address of the handler previously installed |
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| 212 | * |
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| 213 | * Output Parameters: NONE |
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| 214 | * *new_handler - address of the handler previously installed |
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[80f7732] | 215 | * |
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| 216 | * NOTE: |
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[9700578] | 217 | * |
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| 218 | * On the SPARC, there are really only 256 vectors. However, the executive |
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| 219 | * has no easy, fast, reliable way to determine which traps are synchronous |
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| 220 | * and which are asynchronous. By default, synchronous traps return to the |
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| 221 | * instruction which caused the interrupt. So if you install a software |
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| 222 | * trap handler as an executive interrupt handler (which is desirable since |
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| 223 | * RTEMS takes care of window and register issues), then the executive needs |
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| 224 | * to know that the return address is to the trap rather than the instruction |
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| 225 | * following the trap. |
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| 226 | * |
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| 227 | * So vectors 0 through 255 are treated as regular asynchronous traps which |
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| 228 | * provide the "correct" return address. Vectors 256 through 512 are assumed |
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| 229 | * by the executive to be synchronous and to require that the return address |
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| 230 | * be fudged. |
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| 231 | * |
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| 232 | * If you use this mechanism to install a trap handler which must reexecute |
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| 233 | * the instruction which caused the trap, then it should be installed as |
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| 234 | * an asynchronous trap. This will avoid the executive changing the return |
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| 235 | * address. |
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| 236 | */ |
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[80f7732] | 237 | |
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[9700578] | 238 | void _CPU_ISR_install_raw_handler( |
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[2a0a6851] | 239 | uint32_t vector, |
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[9700578] | 240 | proc_ptr new_handler, |
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| 241 | proc_ptr *old_handler |
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| 242 | ) |
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| 243 | { |
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[2a0a6851] | 244 | uint32_t real_vector; |
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[9700578] | 245 | CPU_Trap_table_entry *tbr; |
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| 246 | CPU_Trap_table_entry *slot; |
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[2a0a6851] | 247 | uint32_t u32_tbr; |
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| 248 | uint32_t u32_handler; |
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[9700578] | 249 | |
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| 250 | /* |
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| 251 | * Get the "real" trap number for this vector ignoring the synchronous |
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| 252 | * versus asynchronous indicator included with our vector numbers. |
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| 253 | */ |
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| 254 | |
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| 255 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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| 256 | |
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| 257 | /* |
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| 258 | * Get the current base address of the trap table and calculate a pointer |
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| 259 | * to the slot we are interested in. |
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| 260 | */ |
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| 261 | |
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| 262 | sparc_get_tbr( u32_tbr ); |
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| 263 | |
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| 264 | u32_tbr &= 0xfffff000; |
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| 265 | |
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| 266 | tbr = (CPU_Trap_table_entry *) u32_tbr; |
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| 267 | |
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| 268 | slot = &tbr[ real_vector ]; |
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| 269 | |
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| 270 | /* |
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| 271 | * Get the address of the old_handler from the trap table. |
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| 272 | * |
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| 273 | * NOTE: The old_handler returned will be bogus if it does not follow |
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| 274 | * the RTEMS model. |
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| 275 | */ |
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| 276 | |
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| 277 | #define HIGH_BITS_MASK 0xFFFFFC00 |
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| 278 | #define HIGH_BITS_SHIFT 10 |
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| 279 | #define LOW_BITS_MASK 0x000003FF |
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| 280 | |
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| 281 | if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) { |
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[80f7732] | 282 | u32_handler = |
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[49cff0fc] | 283 | (slot->sethi_of_handler_to_l4 << HIGH_BITS_SHIFT) | |
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[9700578] | 284 | (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK); |
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| 285 | *old_handler = (proc_ptr) u32_handler; |
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| 286 | } else |
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| 287 | *old_handler = 0; |
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| 288 | |
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| 289 | /* |
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| 290 | * Copy the template to the slot and then fix it. |
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| 291 | */ |
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| 292 | |
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| 293 | *slot = _CPU_Trap_slot_template; |
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| 294 | |
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[df4fcaa] | 295 | u32_handler = (uint32_t) new_handler; |
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[9700578] | 296 | |
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| 297 | slot->mov_vector_l3 |= vector; |
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[80f7732] | 298 | slot->sethi_of_handler_to_l4 |= |
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[9700578] | 299 | (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT; |
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| 300 | slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK); |
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[477e2d19] | 301 | |
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[bba83e5] | 302 | /* |
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| 303 | * There is no instruction cache snooping, so we need to invalidate |
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| 304 | * the instruction cache to make sure that the processor sees the |
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| 305 | * changes to the trap table. This step is required on both single- |
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| 306 | * and multiprocessor systems. |
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| 307 | * |
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| 308 | * In a SMP configuration a change to the trap table might be |
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| 309 | * missed by other cores. If the system state is up, the other |
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| 310 | * cores can be notified using SMP messages that they need to |
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| 311 | * flush their icache. If the up state has not been reached |
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| 312 | * there is no need to notify other cores. They will do an |
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| 313 | * automatic flush of the icache just after entering the up |
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| 314 | * state, but before enabling interrupts. |
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| 315 | */ |
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[477e2d19] | 316 | rtems_cache_invalidate_entire_instruction(); |
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[9700578] | 317 | } |
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| 318 | |
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[c62d36f] | 319 | void _CPU_ISR_install_vector( |
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[2a0a6851] | 320 | uint32_t vector, |
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[c62d36f] | 321 | proc_ptr new_handler, |
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| 322 | proc_ptr *old_handler |
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| 323 | ) |
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| 324 | { |
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[2a0a6851] | 325 | uint32_t real_vector; |
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[9700578] | 326 | proc_ptr ignored; |
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| 327 | |
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| 328 | /* |
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| 329 | * Get the "real" trap number for this vector ignoring the synchronous |
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| 330 | * versus asynchronous indicator included with our vector numbers. |
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| 331 | */ |
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| 332 | |
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| 333 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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[c62d36f] | 334 | |
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| 335 | /* |
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[9700578] | 336 | * Return the previous ISR handler. |
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[c62d36f] | 337 | */ |
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| 338 | |
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[9700578] | 339 | *old_handler = _ISR_Vector_table[ real_vector ]; |
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| 340 | |
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[c62d36f] | 341 | /* |
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[9700578] | 342 | * Install the wrapper so this ISR can be invoked properly. |
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[c62d36f] | 343 | */ |
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| 344 | |
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[9700578] | 345 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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[c62d36f] | 346 | |
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[9700578] | 347 | /* |
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| 348 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 349 | * be used by the _ISR_Handler so the user gets control. |
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| 350 | */ |
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[c62d36f] | 351 | |
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[9700578] | 352 | _ISR_Vector_table[ real_vector ] = new_handler; |
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[c62d36f] | 353 | } |
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| 354 | |
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| 355 | void _CPU_Context_Initialize( |
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[9700578] | 356 | Context_Control *the_context, |
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[2a0a6851] | 357 | uint32_t *stack_base, |
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| 358 | uint32_t size, |
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| 359 | uint32_t new_level, |
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[9700578] | 360 | void *entry_point, |
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[022851a] | 361 | bool is_fp, |
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| 362 | void *tls_area |
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[c62d36f] | 363 | ) |
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| 364 | { |
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[2a0a6851] | 365 | uint32_t stack_high; /* highest "stack aligned" address */ |
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| 366 | uint32_t tmp_psr; |
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[80f7732] | 367 | |
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[c62d36f] | 368 | /* |
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| 369 | * On CPUs with stacks which grow down (i.e. SPARC), we build the stack |
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[80f7732] | 370 | * based on the stack_high address. |
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[c62d36f] | 371 | */ |
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[80f7732] | 372 | |
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[df4fcaa] | 373 | stack_high = ((uint32_t)(stack_base) + size); |
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[9700578] | 374 | stack_high &= ~(CPU_STACK_ALIGNMENT - 1); |
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[80f7732] | 375 | |
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[c62d36f] | 376 | /* |
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[9700578] | 377 | * See the README in this directory for a diagram of the stack. |
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[c62d36f] | 378 | */ |
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[80f7732] | 379 | |
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[df4fcaa] | 380 | the_context->o7 = ((uint32_t) entry_point) - 8; |
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[427dcee] | 381 | the_context->o6_sp = stack_high - SPARC_MINIMUM_STACK_FRAME_SIZE; |
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[48816d7] | 382 | the_context->i6_fp = 0; |
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[c62d36f] | 383 | |
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[9700578] | 384 | /* |
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| 385 | * Build the PSR for the task. Most everything can be 0 and the |
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| 386 | * CWP is corrected during the context switch. |
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| 387 | * |
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| 388 | * The EF bit determines if the floating point unit is available. |
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| 389 | * The FPU is ONLY enabled if the context is associated with an FP task |
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| 390 | * and this SPARC model has an FPU. |
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| 391 | */ |
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[c62d36f] | 392 | |
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| 393 | sparc_get_psr( tmp_psr ); |
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[9700578] | 394 | tmp_psr &= ~SPARC_PSR_PIL_MASK; |
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| 395 | tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK; |
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| 396 | tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */ |
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[80f7732] | 397 | |
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[78cac9b] | 398 | /* _CPU_Context_restore_heir() relies on this */ |
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| 399 | _Assert( ( tmp_psr & SPARC_PSR_ET_MASK ) != 0 ); |
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| 400 | |
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[9700578] | 401 | #if (SPARC_HAS_FPU == 1) |
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| 402 | /* |
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| 403 | * If this bit is not set, then a task gets a fault when it accesses |
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| 404 | * a floating point register. This is a nice way to detect floating |
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| 405 | * point tasks which are not currently declared as such. |
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| 406 | */ |
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| 407 | |
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| 408 | if ( is_fp ) |
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| 409 | tmp_psr |= SPARC_PSR_EF_MASK; |
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| 410 | #endif |
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| 411 | the_context->psr = tmp_psr; |
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[a32835a3] | 412 | |
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| 413 | /* |
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| 414 | * Since THIS thread is being created, there is no way that THIS |
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| 415 | * thread can have an _ISR_Dispatch stack frame on its stack. |
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| 416 | */ |
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| 417 | the_context->isr_dispatch_disable = 0; |
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[022851a] | 418 | |
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| 419 | if ( tls_area != NULL ) { |
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[320faf8e] | 420 | void *tcb = _TLS_TCB_after_TLS_block_initialize( tls_area ); |
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[022851a] | 421 | |
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| 422 | the_context->g7 = (uintptr_t) tcb; |
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| 423 | } |
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[c62d36f] | 424 | } |
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