[c62d36f] | 1 | /* |
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| 2 | * SPARC Dependent Source |
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| 3 | * |
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[03f2154e] | 4 | * COPYRIGHT (c) 1989-1997. |
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[c4808ca] | 5 | * On-Line Applications Research Corporation (OAR). |
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[03f2154e] | 6 | * Copyright assigned to U.S. Government, 1994. |
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[c4808ca] | 7 | * |
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[03f2154e] | 8 | * The license and distribution terms for this file may in |
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| 9 | * the file LICENSE in this distribution or at |
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| 10 | * http://www.OARcorp.com/rtems/license.html. |
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[c4808ca] | 11 | * |
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| 12 | * Ported to ERC32 implementation of the SPARC by On-Line Applications |
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| 13 | * Research Corporation (OAR) under contract to the European Space |
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| 14 | * Agency (ESA). |
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| 15 | * |
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| 16 | * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. |
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| 17 | * European Space Agency. |
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| 18 | * |
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[c62d36f] | 19 | * $Id$ |
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| 20 | */ |
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| 21 | |
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| 22 | #include <rtems/system.h> |
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| 23 | #include <rtems/score/isr.h> |
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| 24 | |
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[9700578] | 25 | #if defined(erc32) |
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| 26 | #include <erc32.h> |
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| 27 | #endif |
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| 28 | |
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| 29 | /* |
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| 30 | * This initializes the set of opcodes placed in each trap |
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| 31 | * table entry. The routine which installs a handler is responsible |
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| 32 | * for filling in the fields for the _handler address and the _vector |
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| 33 | * trap type. |
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| 34 | * |
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| 35 | * The constants following this structure are masks for the fields which |
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| 36 | * must be filled in when the handler is installed. |
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| 37 | */ |
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| 38 | |
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| 39 | const CPU_Trap_table_entry _CPU_Trap_slot_template = { |
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| 40 | 0xa1480000, /* mov %psr, %l0 */ |
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| 41 | 0x29000000, /* sethi %hi(_handler), %l4 */ |
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| 42 | 0x81c52000, /* jmp %l4 + %lo(_handler) */ |
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| 43 | 0xa6102000 /* mov _vector, %l3 */ |
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| 44 | }; |
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| 45 | |
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| 46 | /*PAGE |
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| 47 | * |
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| 48 | * _CPU_Initialize |
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[c62d36f] | 49 | * |
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| 50 | * This routine performs processor dependent initialization. |
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| 51 | * |
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[9700578] | 52 | * Input Parameters: |
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[c62d36f] | 53 | * cpu_table - CPU table to initialize |
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| 54 | * thread_dispatch - address of disptaching routine |
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[9700578] | 55 | * |
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| 56 | * Output Parameters: NONE |
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| 57 | * |
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| 58 | * NOTE: There is no need to save the pointer to the thread dispatch routine. |
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| 59 | * The SPARC's assembly code can reference it directly with no problems. |
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[c62d36f] | 60 | */ |
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| 61 | |
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| 62 | void _CPU_Initialize( |
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| 63 | rtems_cpu_table *cpu_table, |
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[9700578] | 64 | void (*thread_dispatch) /* ignored on this CPU */ |
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[c62d36f] | 65 | ) |
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| 66 | { |
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[9700578] | 67 | void *pointer; |
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[e1a06d1b] | 68 | |
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| 69 | #ifndef NO_TABLE_MOVE |
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[9700578] | 70 | unsigned32 trap_table_start; |
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| 71 | unsigned32 tbr_value; |
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| 72 | CPU_Trap_table_entry *old_tbr; |
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| 73 | CPU_Trap_table_entry *trap_table; |
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[c62d36f] | 74 | |
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| 75 | /* |
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[9700578] | 76 | * Install the executive's trap table. All entries from the original |
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| 77 | * trap table are copied into the executive's trap table. This is essential |
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| 78 | * since this preserves critical trap handlers such as the window underflow |
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| 79 | * and overflow handlers. It is the responsibility of the BSP to provide |
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| 80 | * install these in the initial trap table. |
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[c62d36f] | 81 | */ |
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[e1a06d1b] | 82 | |
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[9700578] | 83 | |
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| 84 | trap_table_start = (unsigned32) &_CPU_Trap_Table_area; |
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| 85 | if (trap_table_start & (SPARC_TRAP_TABLE_ALIGNMENT-1)) |
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| 86 | trap_table_start = (trap_table_start + SPARC_TRAP_TABLE_ALIGNMENT) & |
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| 87 | ~(SPARC_TRAP_TABLE_ALIGNMENT-1); |
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| 88 | |
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| 89 | trap_table = (CPU_Trap_table_entry *) trap_table_start; |
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| 90 | |
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| 91 | sparc_get_tbr( tbr_value ); |
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[c62d36f] | 92 | |
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[9700578] | 93 | old_tbr = (CPU_Trap_table_entry *) (tbr_value & 0xfffff000); |
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| 94 | |
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| 95 | memcpy( trap_table, (void *) old_tbr, 256 * sizeof( CPU_Trap_table_entry ) ); |
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| 96 | |
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| 97 | sparc_set_tbr( trap_table_start ); |
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[c62d36f] | 98 | |
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[e1a06d1b] | 99 | #endif |
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| 100 | |
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[c62d36f] | 101 | /* |
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[9700578] | 102 | * This seems to be the most appropriate way to obtain an initial |
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| 103 | * FP context on the SPARC. The NULL fp context is copied it to |
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| 104 | * the task's FP context during Context_Initialize. |
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[c62d36f] | 105 | */ |
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| 106 | |
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| 107 | pointer = &_CPU_Null_fp_context; |
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| 108 | _CPU_Context_save_fp( &pointer ); |
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| 109 | |
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[9700578] | 110 | /* |
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| 111 | * Grab our own copy of the user's CPU table. |
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| 112 | */ |
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| 113 | |
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[c62d36f] | 114 | _CPU_Table = *cpu_table; |
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[9700578] | 115 | |
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| 116 | #if defined(erc32) |
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| 117 | |
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| 118 | /* |
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| 119 | * ERC32 specific initialization |
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| 120 | */ |
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| 121 | |
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| 122 | _ERC32_MEC_Timer_Control_Mirror = 0; |
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| 123 | ERC32_MEC.Timer_Control = 0; |
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| 124 | |
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| 125 | ERC32_MEC.Control |= ERC32_CONFIGURATION_POWER_DOWN_ALLOWED; |
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| 126 | |
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| 127 | #endif |
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| 128 | |
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[c62d36f] | 129 | } |
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| 130 | |
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| 131 | /*PAGE |
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| 132 | * |
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| 133 | * _CPU_ISR_Get_level |
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[9700578] | 134 | * |
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| 135 | * Input Parameters: NONE |
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| 136 | * |
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| 137 | * Output Parameters: |
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| 138 | * returns the current interrupt level (PIL field of the PSR) |
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[c62d36f] | 139 | */ |
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| 140 | |
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| 141 | unsigned32 _CPU_ISR_Get_level( void ) |
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| 142 | { |
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| 143 | unsigned32 level; |
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| 144 | |
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| 145 | sparc_get_interrupt_level( level ); |
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| 146 | |
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| 147 | return level; |
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| 148 | } |
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| 149 | |
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[9700578] | 150 | /*PAGE |
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| 151 | * |
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| 152 | * _CPU_ISR_install_raw_handler |
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| 153 | * |
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| 154 | * This routine installs the specified handler as a "raw" non-executive |
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| 155 | * supported trap handler (a.k.a. interrupt service routine). |
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| 156 | * |
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| 157 | * Input Parameters: |
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| 158 | * vector - trap table entry number plus synchronous |
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| 159 | * vs. asynchronous information |
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| 160 | * new_handler - address of the handler to be installed |
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| 161 | * old_handler - pointer to an address of the handler previously installed |
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| 162 | * |
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| 163 | * Output Parameters: NONE |
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| 164 | * *new_handler - address of the handler previously installed |
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| 165 | * |
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| 166 | * NOTE: |
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| 167 | * |
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| 168 | * On the SPARC, there are really only 256 vectors. However, the executive |
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| 169 | * has no easy, fast, reliable way to determine which traps are synchronous |
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| 170 | * and which are asynchronous. By default, synchronous traps return to the |
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| 171 | * instruction which caused the interrupt. So if you install a software |
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| 172 | * trap handler as an executive interrupt handler (which is desirable since |
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| 173 | * RTEMS takes care of window and register issues), then the executive needs |
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| 174 | * to know that the return address is to the trap rather than the instruction |
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| 175 | * following the trap. |
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| 176 | * |
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| 177 | * So vectors 0 through 255 are treated as regular asynchronous traps which |
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| 178 | * provide the "correct" return address. Vectors 256 through 512 are assumed |
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| 179 | * by the executive to be synchronous and to require that the return address |
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| 180 | * be fudged. |
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| 181 | * |
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| 182 | * If you use this mechanism to install a trap handler which must reexecute |
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| 183 | * the instruction which caused the trap, then it should be installed as |
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| 184 | * an asynchronous trap. This will avoid the executive changing the return |
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| 185 | * address. |
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| 186 | */ |
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| 187 | |
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| 188 | void _CPU_ISR_install_raw_handler( |
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| 189 | unsigned32 vector, |
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| 190 | proc_ptr new_handler, |
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| 191 | proc_ptr *old_handler |
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| 192 | ) |
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| 193 | { |
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| 194 | unsigned32 real_vector; |
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| 195 | CPU_Trap_table_entry *tbr; |
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| 196 | CPU_Trap_table_entry *slot; |
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| 197 | unsigned32 u32_tbr; |
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| 198 | unsigned32 u32_handler; |
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| 199 | |
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| 200 | /* |
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| 201 | * Get the "real" trap number for this vector ignoring the synchronous |
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| 202 | * versus asynchronous indicator included with our vector numbers. |
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| 203 | */ |
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| 204 | |
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| 205 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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| 206 | |
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| 207 | /* |
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| 208 | * Get the current base address of the trap table and calculate a pointer |
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| 209 | * to the slot we are interested in. |
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| 210 | */ |
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| 211 | |
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| 212 | sparc_get_tbr( u32_tbr ); |
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| 213 | |
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| 214 | u32_tbr &= 0xfffff000; |
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| 215 | |
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| 216 | tbr = (CPU_Trap_table_entry *) u32_tbr; |
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| 217 | |
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| 218 | slot = &tbr[ real_vector ]; |
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| 219 | |
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| 220 | /* |
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| 221 | * Get the address of the old_handler from the trap table. |
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| 222 | * |
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| 223 | * NOTE: The old_handler returned will be bogus if it does not follow |
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| 224 | * the RTEMS model. |
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| 225 | */ |
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| 226 | |
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| 227 | #define HIGH_BITS_MASK 0xFFFFFC00 |
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| 228 | #define HIGH_BITS_SHIFT 10 |
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| 229 | #define LOW_BITS_MASK 0x000003FF |
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| 230 | |
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| 231 | if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) { |
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| 232 | u32_handler = |
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| 233 | ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) | |
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| 234 | (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK); |
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| 235 | *old_handler = (proc_ptr) u32_handler; |
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| 236 | } else |
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| 237 | *old_handler = 0; |
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| 238 | |
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| 239 | /* |
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| 240 | * Copy the template to the slot and then fix it. |
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| 241 | */ |
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| 242 | |
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| 243 | *slot = _CPU_Trap_slot_template; |
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| 244 | |
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| 245 | u32_handler = (unsigned32) new_handler; |
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| 246 | |
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| 247 | slot->mov_vector_l3 |= vector; |
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| 248 | slot->sethi_of_handler_to_l4 |= |
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| 249 | (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT; |
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| 250 | slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK); |
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| 251 | } |
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| 252 | |
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| 253 | /*PAGE |
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| 254 | * |
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| 255 | * _CPU_ISR_install_vector |
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[c62d36f] | 256 | * |
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| 257 | * This kernel routine installs the RTEMS handler for the |
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| 258 | * specified vector. |
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| 259 | * |
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| 260 | * Input parameters: |
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[9700578] | 261 | * vector - interrupt vector number |
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| 262 | * new_handler - replacement ISR for this vector number |
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| 263 | * old_handler - pointer to former ISR for this vector number |
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[c62d36f] | 264 | * |
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[9700578] | 265 | * Output parameters: |
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| 266 | * *old_handler - former ISR for this vector number |
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[c62d36f] | 267 | * |
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| 268 | */ |
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| 269 | |
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| 270 | void _CPU_ISR_install_vector( |
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| 271 | unsigned32 vector, |
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| 272 | proc_ptr new_handler, |
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| 273 | proc_ptr *old_handler |
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| 274 | ) |
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| 275 | { |
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[9700578] | 276 | unsigned32 real_vector; |
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| 277 | proc_ptr ignored; |
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| 278 | |
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| 279 | /* |
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| 280 | * Get the "real" trap number for this vector ignoring the synchronous |
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| 281 | * versus asynchronous indicator included with our vector numbers. |
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| 282 | */ |
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| 283 | |
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| 284 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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[c62d36f] | 285 | |
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| 286 | /* |
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[9700578] | 287 | * Return the previous ISR handler. |
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[c62d36f] | 288 | */ |
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| 289 | |
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[9700578] | 290 | *old_handler = _ISR_Vector_table[ real_vector ]; |
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| 291 | |
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[c62d36f] | 292 | /* |
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[9700578] | 293 | * Install the wrapper so this ISR can be invoked properly. |
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[c62d36f] | 294 | */ |
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| 295 | |
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[9700578] | 296 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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[c62d36f] | 297 | |
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[9700578] | 298 | /* |
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| 299 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 300 | * be used by the _ISR_Handler so the user gets control. |
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| 301 | */ |
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[c62d36f] | 302 | |
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[9700578] | 303 | _ISR_Vector_table[ real_vector ] = new_handler; |
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[c62d36f] | 304 | } |
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| 305 | |
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| 306 | /*PAGE |
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| 307 | * |
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| 308 | * _CPU_Context_Initialize |
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[9700578] | 309 | * |
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| 310 | * This kernel routine initializes the basic non-FP context area associated |
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| 311 | * with each thread. |
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| 312 | * |
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| 313 | * Input parameters: |
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| 314 | * the_context - pointer to the context area |
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| 315 | * stack_base - address of memory for the SPARC |
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| 316 | * size - size in bytes of the stack area |
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| 317 | * new_level - interrupt level for this context area |
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| 318 | * entry_point - the starting execution point for this this context |
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| 319 | * is_fp - TRUE if this context is associated with an FP thread |
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| 320 | * |
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| 321 | * Output parameters: NONE |
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[c62d36f] | 322 | */ |
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| 323 | |
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| 324 | void _CPU_Context_Initialize( |
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[9700578] | 325 | Context_Control *the_context, |
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| 326 | unsigned32 *stack_base, |
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| 327 | unsigned32 size, |
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| 328 | unsigned32 new_level, |
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| 329 | void *entry_point, |
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| 330 | boolean is_fp |
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[c62d36f] | 331 | ) |
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| 332 | { |
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[9700578] | 333 | unsigned32 stack_high; /* highest "stack aligned" address */ |
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| 334 | unsigned32 the_size; |
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[c62d36f] | 335 | unsigned32 tmp_psr; |
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| 336 | |
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| 337 | /* |
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| 338 | * On CPUs with stacks which grow down (i.e. SPARC), we build the stack |
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[9700578] | 339 | * based on the stack_high address. |
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[c62d36f] | 340 | */ |
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| 341 | |
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[9700578] | 342 | stack_high = ((unsigned32)(stack_base) + size); |
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| 343 | stack_high &= ~(CPU_STACK_ALIGNMENT - 1); |
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[c62d36f] | 344 | |
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[9700578] | 345 | the_size = size & ~(CPU_STACK_ALIGNMENT - 1); |
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[c62d36f] | 346 | |
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| 347 | /* |
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[9700578] | 348 | * See the README in this directory for a diagram of the stack. |
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[c62d36f] | 349 | */ |
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| 350 | |
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[9700578] | 351 | the_context->o7 = ((unsigned32) entry_point) - 8; |
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| 352 | the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE; |
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| 353 | the_context->i6_fp = stack_high; |
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[c62d36f] | 354 | |
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[9700578] | 355 | /* |
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| 356 | * Build the PSR for the task. Most everything can be 0 and the |
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| 357 | * CWP is corrected during the context switch. |
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| 358 | * |
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| 359 | * The EF bit determines if the floating point unit is available. |
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| 360 | * The FPU is ONLY enabled if the context is associated with an FP task |
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| 361 | * and this SPARC model has an FPU. |
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| 362 | */ |
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[c62d36f] | 363 | |
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| 364 | sparc_get_psr( tmp_psr ); |
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[9700578] | 365 | tmp_psr &= ~SPARC_PSR_PIL_MASK; |
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| 366 | tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK; |
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| 367 | tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */ |
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| 368 | |
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| 369 | #if (SPARC_HAS_FPU == 1) |
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| 370 | /* |
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| 371 | * If this bit is not set, then a task gets a fault when it accesses |
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| 372 | * a floating point register. This is a nice way to detect floating |
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| 373 | * point tasks which are not currently declared as such. |
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| 374 | */ |
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| 375 | |
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| 376 | if ( is_fp ) |
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| 377 | tmp_psr |= SPARC_PSR_EF_MASK; |
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| 378 | #endif |
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| 379 | the_context->psr = tmp_psr; |
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[c62d36f] | 380 | } |
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| 381 | |
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| 382 | /*PAGE |
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| 383 | * |
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[75f09e5] | 384 | * _CPU_Thread_Idle_body |
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[c62d36f] | 385 | * |
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[9700578] | 386 | * Some SPARC implementations have low power, sleep, or idle modes. This |
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| 387 | * tries to take advantage of those models. |
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| 388 | */ |
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| 389 | |
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| 390 | #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) |
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| 391 | |
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| 392 | /* |
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| 393 | * This is the implementation for the erc32. |
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[c62d36f] | 394 | * |
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[9700578] | 395 | * NOTE: Low power mode was enabled at initialization time. |
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[c62d36f] | 396 | */ |
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| 397 | |
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[9700578] | 398 | #if defined(erc32) |
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| 399 | |
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[75f09e5] | 400 | void _CPU_Thread_Idle_body( void ) |
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[c62d36f] | 401 | { |
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[9700578] | 402 | while (1) { |
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| 403 | ERC32_MEC.Power_Down = 0; /* value is irrelevant */ |
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| 404 | } |
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[c62d36f] | 405 | } |
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[9700578] | 406 | |
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| 407 | #endif |
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| 408 | |
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| 409 | #endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ |
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