[9700578] | 1 | # |
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| 2 | # $Id$ |
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| 3 | # |
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| 4 | |
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| 5 | This file discusses SPARC specific issues which are important to |
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| 6 | this port. The primary topics in this file are: |
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| 7 | |
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| 8 | + Global Register Usage |
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| 9 | + Stack Frame |
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| 10 | + EF bit in the PSR |
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| 11 | |
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| 12 | |
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| 13 | Global Register Usage |
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| 14 | ===================== |
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| 15 | |
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| 16 | This information on register usage is based heavily on a comment in the |
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| 17 | file gcc-2.7.0/config/sparc/sparc.h in the the gcc 2.7.0 source. |
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| 18 | |
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| 19 | + g0 is hardwired to 0 |
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| 20 | + On non-v9 systems: |
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| 21 | - g1 is free to use as temporary. |
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| 22 | - g2-g4 are reserved for applications. Gcc normally uses them as |
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| 23 | temporaries, but this can be disabled via the -mno-app-regs option. |
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| 24 | - g5 through g7 are reserved for the operating system. |
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| 25 | + On v9 systems: |
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| 26 | - g1 and g5 are free to use as temporaries. |
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| 27 | - g2-g4 are reserved for applications (the compiler will not normally use |
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| 28 | them, but they can be used as temporaries with -mapp-regs). |
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| 29 | - g6-g7 are reserved for the operating system. |
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| 30 | |
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| 31 | NOTE: As of gcc 2.7.0 register g1 was used in the following scenarios: |
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| 32 | |
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| 33 | + as a temporary by the 64 bit sethi pattern |
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| 34 | + when restoring call-preserved registers in large stack frames |
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| 35 | |
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| 36 | RTEMS places no constraints on the usage of the global registers. Although |
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| 37 | gcc assumes that either g5-g7 (non-V9) or g6-g7 (V9) are reserved for the |
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| 38 | operating system, RTEMS does not assume any special use for them. |
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| 39 | |
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| 40 | |
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| 41 | |
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| 42 | Stack Frame |
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| 43 | =========== |
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| 44 | |
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| 45 | The stack grows downward (i.e. to lower addresses) on the SPARC architecture. |
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| 46 | |
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| 47 | The following is the organization of the stack frame: |
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| 48 | |
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| 49 | |
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| 50 | |
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| 51 | | ............... | |
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| 52 | fp | | |
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| 53 | +-------------------------------+ |
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| 54 | | | |
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| 55 | | Local registers, temporaries, | |
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| 56 | | and saved floats | x bytes |
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| 57 | | | |
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| 58 | sp + x +-------------------------------+ |
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| 59 | | | |
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| 60 | | outgoing parameters past | |
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| 61 | | the sixth one | x bytes |
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| 62 | | | |
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| 63 | sp + 92 +-------------------------------+ * |
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| 64 | | | * |
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| 65 | | area for callee to save | * |
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| 66 | | register arguments | * 24 bytes |
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| 67 | | | * |
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| 68 | sp + 68 +-------------------------------+ * |
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| 69 | | | * |
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| 70 | | structure return pointer | * 4 bytes |
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| 71 | | | * |
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| 72 | sp + 64 +-------------------------------+ * |
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| 73 | | | * |
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| 74 | | local register set | * 32 bytes |
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| 75 | | | * |
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| 76 | sp + 32 +-------------------------------+ * |
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| 77 | | | * |
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| 78 | | input register set | * 32 bytes |
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| 79 | | | * |
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| 80 | sp +-------------------------------+ * |
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| 81 | |
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| 82 | |
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| 83 | * = minimal stack frame |
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| 84 | |
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| 85 | x = optional components |
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| 86 | |
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| 87 | EF bit in the PSR |
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| 88 | ================= |
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| 89 | |
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| 90 | The EF (enable floating point unit) in the PSR is utilized in this port to |
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| 91 | prevent non-floating point tasks from performing floating point |
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| 92 | operations. This bit is maintained as part of the integer context. |
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| 93 | However, the floating point context is switched BEFORE the integer |
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| 94 | context. Thus the EF bit in place at the time of the FP switch may |
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| 95 | indicate that FP operations are disabled. This occurs on certain task |
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| 96 | switches, when the EF bit will be 0 for the outgoing task and thus a fault |
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| 97 | will be generated on the first FP operation of the FP context save. |
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| 98 | |
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| 99 | The remedy for this is to enable FP access as the first step in both the |
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| 100 | save and restore of the FP context area. This bit will be subsequently |
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| 101 | reloaded by the integer context switch. |
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| 102 | |
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| 103 | Two of the scenarios which demonstrate this problem are outlined below: |
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| 104 | |
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| 105 | 1. When the first FP task is switched to. The system tasks are not FP and |
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| 106 | thus would be unable to restore the FP context of the incoming task. |
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| 107 | |
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| 108 | 2. On a deferred FP context switch. In this case, the system might switch |
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| 109 | from FP Task A to non-FP Task B and then to FP Task C. In this scenario, |
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| 110 | the floating point state must technically be saved by a non-FP task. |
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