source: rtems/cpukit/score/cpu/sh/rtems/score/cpu.h @ f82752a4

4.115
Last change on this file since f82752a4 was f82752a4, checked in by Daniel Hellstrom <daniel@…>, on Jun 4, 2014 at 9:23:34 AM

Let CPU/BSP Fatal handler have access to source

Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.

This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.

  • Property mode set to 100644
File size: 27.8 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the Hitachi SH
7 *  processor.
8 *
9 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
10 *           Bernd Becker (becker@faw.uni-ulm.de)
11 *
12 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
13 *
14 *  This program is distributed in the hope that it will be useful,
15 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 *
18 *
19 *  COPYRIGHT (c) 1998-2006.
20 *  On-Line Applications Research Corporation (OAR).
21 *
22 *  The license and distribution terms for this file may be
23 *  found in the file LICENSE in this distribution or at
24 *  http://www.rtems.org/license/LICENSE.
25 */
26
27#ifndef _RTEMS_SCORE_CPU_H
28#define _RTEMS_SCORE_CPU_H
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
34#include <rtems/score/types.h>
35#include <rtems/score/sh.h>
36
37/* conditional compilation parameters */
38
39/*
40 *  Should the calls to _Thread_Enable_dispatch be inlined?
41 *
42 *  If TRUE, then they are inlined.
43 *  If FALSE, then a subroutine call is made.
44 *
45 *  Basically this is an example of the classic trade-off of size
46 *  versus speed.  Inlining the call (TRUE) typically increases the
47 *  size of RTEMS while speeding up the enabling of dispatching.
48 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
49 *  only be 0 or 1 unless you are in an interrupt handler and that
50 *  interrupt handler invokes the executive.]  When not inlined
51 *  something calls _Thread_Enable_dispatch which in turns calls
52 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
53 *  one subroutine call is avoided entirely.]
54 */
55
56#define CPU_INLINE_ENABLE_DISPATCH       FALSE
57
58/*
59 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
60 *  be unrolled one time?  In unrolled each iteration of the loop examines
61 *  two "nodes" on the chain being searched.  Otherwise, only one node
62 *  is examined per iteration.
63 *
64 *  If TRUE, then the loops are unrolled.
65 *  If FALSE, then the loops are not unrolled.
66 *
67 *  The primary factor in making this decision is the cost of disabling
68 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
69 *  body of the loop.  On some CPUs, the flash is more expensive than
70 *  one iteration of the loop body.  In this case, it might be desirable
71 *  to unroll the loop.  It is important to note that on some CPUs, this
72 *  code is the longest interrupt disable period in RTEMS.  So it is
73 *  necessary to strike a balance when setting this parameter.
74 */
75
76#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
77
78/*
79 *  Does the CPU follow the simple vectored interrupt model?
80 *
81 *  If TRUE, then RTEMS allocates the vector table it internally manages.
82 *  If FALSE, then the BSP is assumed to allocate and manage the vector
83 *  table
84 *
85 *  SH Specific Information:
86 *
87 *  XXX document implementation including references if appropriate
88 */
89#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
90
91/*
92 *  Does RTEMS manage a dedicated interrupt stack in software?
93 *
94 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
95 *  If FALSE, nothing is done.
96 *
97 *  If the CPU supports a dedicated interrupt stack in hardware,
98 *  then it is generally the responsibility of the BSP to allocate it
99 *  and set it up.
100 *
101 *  If the CPU does not support a dedicated interrupt stack, then
102 *  the porter has two options: (1) execute interrupts on the
103 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
104 *  interrupt stack.
105 *
106 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
107 *
108 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
109 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
110 *  possible that both are FALSE for a particular CPU.  Although it
111 *  is unclear what that would imply about the interrupt processing
112 *  procedure on that CPU.
113 */
114
115#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
116#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
117
118/*
119 * We define the interrupt stack in the linker script
120 */
121#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
122
123/*
124 *  Does the RTEMS invoke the user's ISR with the vector number and
125 *  a pointer to the saved interrupt frame (1) or just the vector
126 *  number (0)?
127 */
128
129#define CPU_ISR_PASSES_FRAME_POINTER 0
130
131/*
132 *  Does the CPU have hardware floating point?
133 *
134 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
135 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
136 *
137 *  We currently support sh1 only, which has no FPU, other SHes have an FPU
138 *
139 *  The macro name "SH_HAS_FPU" should be made CPU specific.
140 *  It indicates whether or not this CPU model has FP support.  For
141 *  example, it would be possible to have an i386_nofp CPU model
142 *  which set this to false to indicate that you have an i386 without
143 *  an i387 and wish to leave floating point support out of RTEMS.
144 */
145
146#if SH_HAS_FPU
147#define CPU_HARDWARE_FP TRUE
148#define CPU_SOFTWARE_FP FALSE
149#else
150#define CPU_SOFTWARE_FP FALSE
151#define CPU_HARDWARE_FP FALSE
152#endif
153
154/*
155 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
156 *
157 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
158 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
159 *
160 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
161 */
162
163#if SH_HAS_FPU
164#define CPU_ALL_TASKS_ARE_FP     TRUE
165#else
166#define CPU_ALL_TASKS_ARE_FP     FALSE
167#endif
168
169/*
170 *  Should the IDLE task have a floating point context?
171 *
172 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
173 *  and it has a floating point context which is switched in and out.
174 *  If FALSE, then the IDLE task does not have a floating point context.
175 *
176 *  Setting this to TRUE negatively impacts the time required to preempt
177 *  the IDLE task from an interrupt because the floating point context
178 *  must be saved as part of the preemption.
179 */
180
181#if SH_HAS_FPU
182#define CPU_IDLE_TASK_IS_FP     TRUE
183#else
184#define CPU_IDLE_TASK_IS_FP      FALSE
185#endif
186
187/*
188 *  Should the saving of the floating point registers be deferred
189 *  until a context switch is made to another different floating point
190 *  task?
191 *
192 *  If TRUE, then the floating point context will not be stored until
193 *  necessary.  It will remain in the floating point registers and not
194 *  disturned until another floating point task is switched to.
195 *
196 *  If FALSE, then the floating point context is saved when a floating
197 *  point task is switched out and restored when the next floating point
198 *  task is restored.  The state of the floating point registers between
199 *  those two operations is not specified.
200 *
201 *  If the floating point context does NOT have to be saved as part of
202 *  interrupt dispatching, then it should be safe to set this to TRUE.
203 *
204 *  Setting this flag to TRUE results in using a different algorithm
205 *  for deciding when to save and restore the floating point context.
206 *  The deferred FP switch algorithm minimizes the number of times
207 *  the FP context is saved and restored.  The FP context is not saved
208 *  until a context switch is made to another, different FP task.
209 *  Thus in a system with only one FP task, the FP context will never
210 *  be saved or restored.
211 */
212
213#if SH_HAS_FPU
214#define CPU_USE_DEFERRED_FP_SWITCH      FALSE
215#else
216#define CPU_USE_DEFERRED_FP_SWITCH      TRUE
217#endif
218
219/*
220 *  Does this port provide a CPU dependent IDLE task implementation?
221 *
222 *  If TRUE, then the routine _CPU_Thread_Idle_body
223 *  must be provided and is the default IDLE thread body instead of
224 *  _CPU_Thread_Idle_body.
225 *
226 *  If FALSE, then use the generic IDLE thread body if the BSP does
227 *  not provide one.
228 *
229 *  This is intended to allow for supporting processors which have
230 *  a low power or idle mode.  When the IDLE thread is executed, then
231 *  the CPU can be powered down.
232 *
233 *  The order of precedence for selecting the IDLE thread body is:
234 *
235 *    1.  BSP provided
236 *    2.  CPU dependent (if provided)
237 *    3.  generic (if no BSP and no CPU dependent)
238 */
239
240#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
241
242/*
243 *  Does the stack grow up (toward higher addresses) or down
244 *  (toward lower addresses)?
245 *
246 *  If TRUE, then the grows upward.
247 *  If FALSE, then the grows toward smaller addresses.
248 */
249
250#define CPU_STACK_GROWS_UP               FALSE
251
252/*
253 *  The following is the variable attribute used to force alignment
254 *  of critical RTEMS structures.  On some processors it may make
255 *  sense to have these aligned on tighter boundaries than
256 *  the minimum requirements of the compiler in order to have as
257 *  much of the critical data area as possible in a cache line.
258 *
259 *  The placement of this macro in the declaration of the variables
260 *  is based on the syntactically requirements of the GNU C
261 *  "__attribute__" extension.  For example with GNU C, use
262 *  the following to force a structures to a 32 byte boundary.
263 *
264 *      __attribute__ ((aligned (32)))
265 *
266 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
267 *         To benefit from using this, the data must be heavily
268 *         used so it will stay in the cache and used frequently enough
269 *         in the executive to justify turning this on.
270 */
271
272#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned(16)))
273
274#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
275
276/*
277 *  Define what is required to specify how the network to host conversion
278 *  routines are handled.
279 *
280 *  NOTE: SHes can be big or little endian, the default is big endian
281 */
282
283/* __LITTLE_ENDIAN__ is defined if -ml is given to gcc */
284#if defined(__LITTLE_ENDIAN__)
285#define CPU_BIG_ENDIAN                           FALSE
286#define CPU_LITTLE_ENDIAN                        TRUE
287#else
288#define CPU_BIG_ENDIAN                           TRUE
289#define CPU_LITTLE_ENDIAN                        FALSE
290#endif
291
292/*
293 *  The following defines the number of bits actually used in the
294 *  interrupt field of the task mode.  How those bits map to the
295 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
296 */
297
298#define CPU_MODES_INTERRUPT_MASK   0x0000000f
299
300#define CPU_PER_CPU_CONTROL_SIZE 0
301
302/*
303 *  Processor defined structures required for cpukit/score.
304 */
305
306/* may need to put some structures here.  */
307
308typedef struct {
309  /* There is no CPU specific per-CPU state */
310} CPU_Per_CPU_control;
311
312/*
313 * Contexts
314 *
315 *  Generally there are 2 types of context to save.
316 *     1. Interrupt registers to save
317 *     2. Task level registers to save
318 *
319 *  This means we have the following 3 context items:
320 *     1. task level context stuff::  Context_Control
321 *     2. floating point task stuff:: Context_Control_fp
322 *     3. special interrupt level context :: Context_Control_interrupt
323 *
324 *  On some processors, it is cost-effective to save only the callee
325 *  preserved registers during a task context switch.  This means
326 *  that the ISR code needs to save those registers which do not
327 *  persist across function calls.  It is not mandatory to make this
328 *  distinctions between the caller/callee saves registers for the
329 *  purpose of minimizing context saved during task switch and on interrupts.
330 *  If the cost of saving extra registers is minimal, simplicity is the
331 *  choice.  Save the same context on interrupt entry as for tasks in
332 *  this case.
333 *
334 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
335 *  care should be used in designing the context area.
336 *
337 *  On some CPUs with hardware floating point support, the Context_Control_fp
338 *  structure will not be used or it simply consist of an array of a
339 *  fixed number of bytes.   This is done when the floating point context
340 *  is dumped by a "FP save context" type instruction and the format
341 *  is not really defined by the CPU.  In this case, there is no need
342 *  to figure out the exact format -- only the size.  Of course, although
343 *  this is enough information for RTEMS, it is probably not enough for
344 *  a debugger such as gdb.  But that is another problem.
345 */
346
347typedef struct {
348  uint32_t   *r15;      /* stack pointer */
349
350  uint32_t   macl;
351  uint32_t   mach;
352  uint32_t   *pr;
353
354  uint32_t   *r14;      /* frame pointer/call saved */
355
356  uint32_t   r13;       /* call saved */
357  uint32_t   r12;       /* call saved */
358  uint32_t   r11;       /* call saved */
359  uint32_t   r10;       /* call saved */
360  uint32_t   r9;        /* call saved */
361  uint32_t   r8;        /* call saved */
362
363  uint32_t   *r7;       /* arg in */
364  uint32_t   *r6;       /* arg in */
365
366#if 0
367  uint32_t   *r5;       /* arg in */
368  uint32_t   *r4;       /* arg in */
369#endif
370
371  uint32_t   *r3;       /* scratch */
372  uint32_t   *r2;       /* scratch */
373  uint32_t   *r1;       /* scratch */
374
375  uint32_t   *r0;       /* arg return */
376
377  uint32_t   gbr;
378  uint32_t   sr;
379
380} Context_Control;
381
382#define _CPU_Context_Get_SP( _context ) \
383  (_context)->r15
384
385typedef struct {
386#if SH_HAS_FPU
387#ifdef SH4_USE_X_REGISTERS
388  union {
389    float f[16];
390    double d[8];
391  } x;
392#endif
393  union {
394    float f[16];
395    double d[8];
396  } r;
397  float fpul;       /* fp communication register */
398  uint32_t   fpscr; /* fp control register */
399#endif /* SH_HAS_FPU */
400} Context_Control_fp;
401
402typedef struct {
403} CPU_Interrupt_frame;
404
405/*
406 *  This variable is optional.  It is used on CPUs on which it is difficult
407 *  to generate an "uninitialized" FP context.  It is filled in by
408 *  _CPU_Initialize and copied into the task's FP context area during
409 *  _CPU_Context_Initialize.
410 */
411
412#if SH_HAS_FPU
413SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
414#endif
415
416/*
417 *  Nothing prevents the porter from declaring more CPU specific variables.
418 */
419
420/* XXX: if needed, put more variables here */
421SCORE_EXTERN void CPU_delay( uint32_t   microseconds );
422
423/*
424 *  The size of the floating point context area.  On some CPUs this
425 *  will not be a "sizeof" because the format of the floating point
426 *  area is not defined -- only the size is.  This is usually on
427 *  CPUs with a "floating point save context" instruction.
428 */
429
430#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
431
432/*
433 *  Amount of extra stack (above minimum stack size) required by
434 *  MPCI receive server thread.  Remember that in a multiprocessor
435 *  system this thread must exist and be able to process all directives.
436 */
437
438#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
439
440/*
441 *  This defines the number of entries in the ISR_Vector_table managed
442 *  by RTEMS.
443 */
444
445#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
446#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
447
448/*
449 *  This is defined if the port has a special way to report the ISR nesting
450 *  level.  Most ports maintain the variable _ISR_Nest_level.
451 */
452
453#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
454
455/*
456 *  Should be large enough to run all RTEMS tests.  This ensures
457 *  that a "reasonable" small application should not have any problems.
458 *
459 *  We have been able to run the sptests with this value, but have not
460 *  been able to run the tmtest suite.
461 */
462
463#define CPU_STACK_MINIMUM_SIZE          4096
464
465#define CPU_SIZEOF_POINTER 4
466
467/*
468 *  CPU's worst alignment requirement for data types on a byte boundary.  This
469 *  alignment does not take into account the requirements for the stack.
470 */
471#if defined(__SH4__)
472/* FIXME: sh3 and SH3E? */
473#define CPU_ALIGNMENT              8
474#else
475#define CPU_ALIGNMENT              4
476#endif
477
478/*
479 *  This number corresponds to the byte alignment requirement for the
480 *  heap handler.  This alignment requirement may be stricter than that
481 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
482 *  common for the heap to follow the same alignment requirement as
483 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
484 *  then this should be set to CPU_ALIGNMENT.
485 *
486 *  NOTE:  This does not have to be a power of 2.  It does have to
487 *         be greater or equal to than CPU_ALIGNMENT.
488 */
489
490#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
491
492/*
493 *  This number corresponds to the byte alignment requirement for memory
494 *  buffers allocated by the partition manager.  This alignment requirement
495 *  may be stricter than that for the data types alignment specified by
496 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
497 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
498 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
499 *
500 *  NOTE:  This does not have to be a power of 2.  It does have to
501 *         be greater or equal to than CPU_ALIGNMENT.
502 */
503
504#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
505
506/*
507 *  This number corresponds to the byte alignment requirement for the
508 *  stack.  This alignment requirement may be stricter than that for the
509 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
510 *  is strict enough for the stack, then this should be set to 0.
511 *
512 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
513 */
514
515#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
516
517/*
518 *  ISR handler macros
519 */
520
521/*
522 *  Support routine to initialize the RTEMS vector table after it is allocated.
523 *
524 *  SH Specific Information: NONE
525 */
526
527#define _CPU_Initialize_vectors()
528
529/*
530 *  Disable all interrupts for an RTEMS critical section.  The previous
531 *  level is returned in _level.
532 */
533
534#define _CPU_ISR_Disable( _level) \
535  sh_disable_interrupts( _level )
536
537/*
538 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
539 *  This indicates the end of an RTEMS critical section.  The parameter
540 *  _level is not modified.
541 */
542
543#define _CPU_ISR_Enable( _level) \
544   sh_enable_interrupts( _level)
545
546/*
547 *  This temporarily restores the interrupt to _level before immediately
548 *  disabling them again.  This is used to divide long RTEMS critical
549 *  sections into two or more parts.  The parameter _level is not
550 * modified.
551 */
552
553#define _CPU_ISR_Flash( _level) \
554  sh_flash_interrupts( _level)
555
556/*
557 *  Map interrupt level in task mode onto the hardware that the CPU
558 *  actually provides.  Currently, interrupt levels which do not
559 *  map onto the CPU in a generic fashion are undefined.  Someday,
560 *  it would be nice if these were "mapped" by the application
561 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
562 *  8 - 255 would be available for bsp/application specific meaning.
563 *  This could be used to manage a programmable interrupt controller
564 *  via the rtems_task_mode directive.
565 */
566
567#define _CPU_ISR_Set_level( _newlevel) \
568  sh_set_interrupt_level(_newlevel)
569
570uint32_t   _CPU_ISR_Get_level( void );
571
572/* end of ISR handler macros */
573
574/* Context handler macros */
575
576/*
577 *  Initialize the context to a state suitable for starting a
578 *  task after a context restore operation.  Generally, this
579 *  involves:
580 *
581 *     - setting a starting address
582 *     - preparing the stack
583 *     - preparing the stack and frame pointers
584 *     - setting the proper interrupt level in the context
585 *     - initializing the floating point context
586 *
587 *  This routine generally does not set any unnecessary register
588 *  in the context.  The state of the "general data" registers is
589 *  undefined at task start time.
590 *
591 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
592 *        point thread.  This is typically only used on CPUs where the
593 *        FPU may be easily disabled by software such as on the SPARC
594 *        where the PSR contains an enable FPU bit.
595 */
596
597/*
598 * FIXME: defined as a function for debugging - should be a macro
599 */
600SCORE_EXTERN void _CPU_Context_Initialize(
601  Context_Control       *_the_context,
602  void                  *_stack_base,
603  uint32_t              _size,
604  uint32_t              _isr,
605  void    (*_entry_point)(void),
606  int                   _is_fp,
607  void                  *_tls_area );
608
609/*
610 *  This routine is responsible for somehow restarting the currently
611 *  executing task.  If you are lucky, then all that is necessary
612 *  is restoring the context.  Otherwise, there will need to be
613 *  a special assembly routine which does something special in this
614 *  case.  Context_Restore should work most of the time.  It will
615 *  not work if restarting self conflicts with the stack frame
616 *  assumptions of restoring a context.
617 */
618
619#define _CPU_Context_Restart_self( _the_context ) \
620   _CPU_Context_restore( (_the_context) );
621
622/*
623 *  The purpose of this macro is to allow the initial pointer into
624 *  a floating point context area (used to save the floating point
625 *  context) to be at an arbitrary place in the floating point
626 *  context area.
627 *
628 *  This is necessary because some FP units are designed to have
629 *  their context saved as a stack which grows into lower addresses.
630 *  Other FP units can be saved by simply moving registers into offsets
631 *  from the base of the context area.  Finally some FP units provide
632 *  a "dump context" instruction which could fill in from high to low
633 *  or low to high based on the whim of the CPU designers.
634 */
635
636#define _CPU_Context_Fp_start( _base, _offset ) \
637   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
638
639/*
640 *  This routine initializes the FP context area passed to it to.
641 *  There are a few standard ways in which to initialize the
642 *  floating point context.  The code included for this macro assumes
643 *  that this is a CPU in which a "initial" FP context was saved into
644 *  _CPU_Null_fp_context and it simply copies it to the destination
645 *  context passed to it.
646 *
647 *  Other models include (1) not doing anything, and (2) putting
648 *  a "null FP status word" in the correct place in the FP context.
649 *  SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have.
650 */
651
652#if SH_HAS_FPU
653#define _CPU_Context_Initialize_fp( _destination ) \
654  do { \
655     *(*(_destination)) = _CPU_Null_fp_context;\
656  } while(0)
657#else
658#define _CPU_Context_Initialize_fp( _destination ) \
659  {  }
660#endif
661
662/* end of Context handler macros */
663
664/* Fatal Error manager macros */
665
666/*
667 * FIXME: Trap32 ???
668 *
669 *  This routine copies _error into a known place -- typically a stack
670 *  location or a register, optionally disables interrupts, and
671 *  invokes a Trap32 Instruction which returns to the breakpoint
672 *  routine of cmon.
673 */
674
675#ifdef BSP_FATAL_HALT
676  /* we manage the fatal error in the board support package */
677  void bsp_fatal_halt( uint32_t   _error);
678#define _CPU_Fatal_halt( _source, _error ) bsp_fatal_halt( _error)
679#else
680#define _CPU_Fatal_halt( _source, _error)\
681{ \
682  __asm__ volatile("mov.l %0,r0"::"m" (_error)); \
683  __asm__ volatile("mov #1, r4"); \
684  __asm__ volatile("trapa #34"); \
685}
686#endif
687
688/* end of Fatal Error manager macros */
689
690/* Bitfield handler macros */
691
692/*
693 *  This routine sets _output to the bit number of the first bit
694 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Word.
695 *  This type may be either 16 or 32 bits wide although only the 16
696 *  least significant bits will be used.
697 *
698 *  There are a number of variables in using a "find first bit" type
699 *  instruction.
700 *
701 *    (1) What happens when run on a value of zero?
702 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
703 *    (3) The numbering may be zero or one based.
704 *    (4) The "find first bit" instruction may search from MSB or LSB.
705 *
706 *  RTEMS guarantees that (1) will never happen so it is not a concern.
707 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
708 *  _CPU_Priority_bits_index().  These three form a set of routines
709 *  which must logically operate together.  Bits in the _value are
710 *  set and cleared based on masks built by _CPU_Priority_mask().
711 *  The basic major and minor values calculated by _Priority_Major()
712 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
713 *  to properly range between the values returned by the "find first bit"
714 *  instruction.  This makes it possible for _Priority_Get_highest() to
715 *  calculate the major and directly index into the minor table.
716 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
717 *  is the first bit found.
718 *
719 *  This entire "find first bit" and mapping process depends heavily
720 *  on the manner in which a priority is broken into a major and minor
721 *  components with the major being the 4 MSB of a priority and minor
722 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
723 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
724 *  to the lowest priority.
725 *
726 *  If your CPU does not have a "find first bit" instruction, then
727 *  there are ways to make do without it.  Here are a handful of ways
728 *  to implement this in software:
729 *
730 *    - a series of 16 bit test instructions
731 *    - a "binary search using if's"
732 *    - _number = 0
733 *      if _value > 0x00ff
734 *        _value >>=8
735 *        _number = 8;
736 *
737 *      if _value > 0x0000f
738 *        _value >=8
739 *        _number += 4
740 *
741 *      _number += bit_set_table[ _value ]
742 *
743 *    where bit_set_table[ 16 ] has values which indicate the first
744 *      bit set
745 */
746
747#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
748#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
749
750#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
751
752extern uint8_t   _bit_set_table[];
753
754#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
755  { \
756      _output = 0;\
757      if(_value > 0x00ff) \
758      { _value >>= 8; _output = 8; } \
759      if(_value > 0x000f) \
760        { _output += 4; _value >>= 4; } \
761      _output += _bit_set_table[ _value]; }
762
763#endif
764
765/* end of Bitfield handler macros */
766
767/*
768 *  This routine builds the mask which corresponds to the bit fields
769 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
770 *  for that routine.
771 */
772
773#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
774
775#define _CPU_Priority_Mask( _bit_number ) \
776  ( 1 << (_bit_number) )
777
778#endif
779
780/*
781 *  This routine translates the bit numbers returned by
782 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
783 *  a major or minor component of a priority.  See the discussion
784 *  for that routine.
785 */
786
787#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
788
789#define _CPU_Priority_bits_index( _priority ) \
790  (_priority)
791
792#endif
793
794/* end of Priority handler macros */
795
796/* functions */
797
798/*
799 *  @brief CPU Initialize
800 *
801 *  _CPU_Initialize
802 *
803 *  This routine performs CPU dependent initialization.
804 */
805void _CPU_Initialize(void);
806
807/*
808 *  _CPU_ISR_install_raw_handler
809 *
810 *  This routine installs a "raw" interrupt handler directly into the
811 *  processor's vector table.
812 */
813
814void _CPU_ISR_install_raw_handler(
815  uint32_t    vector,
816  proc_ptr    new_handler,
817  proc_ptr   *old_handler
818);
819
820/*
821 *  _CPU_ISR_install_vector
822 *
823 *  This routine installs an interrupt vector.
824 */
825
826void _CPU_ISR_install_vector(
827  uint32_t    vector,
828  proc_ptr    new_handler,
829  proc_ptr   *old_handler
830);
831
832/*
833 *  _CPU_Install_interrupt_stack
834 *
835 *  This routine installs the hardware interrupt stack pointer.
836 *
837 *  NOTE:  It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
838 *         is TRUE.
839 */
840
841void _CPU_Install_interrupt_stack( void );
842
843/*
844 *  _CPU_Thread_Idle_body
845 *
846 *  This routine is the CPU dependent IDLE thread body.
847 *
848 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
849 *         is TRUE.
850 */
851
852void *_CPU_Thread_Idle_body( uintptr_t ignored );
853
854/*
855 *  _CPU_Context_switch
856 *
857 *  This routine switches from the run context to the heir context.
858 */
859
860void _CPU_Context_switch(
861  Context_Control  *run,
862  Context_Control  *heir
863);
864
865/*
866 *  _CPU_Context_restore
867 *
868 *  This routine is generally used only to restart self in an
869 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
870 */
871
872void _CPU_Context_restore(
873  Context_Control *new_context
874) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
875
876/*
877 *  @brief This routine saves the floating point context passed to it.
878 *
879 *  _CPU_Context_save_fp
880 *
881 */
882void _CPU_Context_save_fp(
883  Context_Control_fp **fp_context_ptr
884);
885
886/*
887 *  @brief This routine restores the floating point context passed to it.
888 *
889 *  _CPU_Context_restore_fp
890 *
891 */
892void _CPU_Context_restore_fp(
893  Context_Control_fp **fp_context_ptr
894);
895
896static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
897{
898  /* TODO */
899}
900
901static inline void _CPU_Context_validate( uintptr_t pattern )
902{
903  while (1) {
904    /* TODO */
905  }
906}
907
908/* FIXME */
909typedef CPU_Interrupt_frame CPU_Exception_frame;
910
911void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
912
913typedef uint32_t CPU_Counter_ticks;
914
915CPU_Counter_ticks _CPU_Counter_read( void );
916
917static inline CPU_Counter_ticks _CPU_Counter_difference(
918  CPU_Counter_ticks second,
919  CPU_Counter_ticks first
920)
921{
922  return second - first;
923}
924
925#ifdef __cplusplus
926}
927#endif
928
929#endif
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