source: rtems/cpukit/score/cpu/sh/rtems/score/cpu.h @ ae87ce4

4.104.114.84.9
Last change on this file since ae87ce4 was ae87ce4, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 3, 2002 at 2:06:54 PM

2001-04-03 Joel Sherrill <joel@…>

  • Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
  • rtems/score/shtypes.h: Removed.
  • rtems/score/types.h: New file via CVS magic.
  • Makefile.am, rtems/score/cpu.h: Account for name change.
  • Property mode set to 100644
File size: 29.3 KB
Line 
1/*
2 *  This include file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 *           Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 *  This program is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 *  COPYRIGHT (c) 1998-2001.
16 *  On-Line Applications Research Corporation (OAR).
17 *
18 *  The license and distribution terms for this file may be
19 *  found in the file LICENSE in this distribution or at
20 *  http://www.OARcorp.com/rtems/license.html.
21 *
22 *  $Id$
23 */
24
25#ifndef _SH_CPU_h
26#define _SH_CPU_h
27
28#ifdef __cplusplus
29extern "C" {
30#endif
31
32#include <rtems/score/sh.h>              /* pick up machine definitions */
33#ifndef ASM
34#include <rtems/score/types.h>
35#endif
36#if 0 && defined(__SH4__)
37#include <rtems/score/sh4_regs.h>
38#endif
39
40/* conditional compilation parameters */
41
42/*
43 *  Should the calls to _Thread_Enable_dispatch be inlined?
44 *
45 *  If TRUE, then they are inlined.
46 *  If FALSE, then a subroutine call is made.
47 *
48 *  Basically this is an example of the classic trade-off of size
49 *  versus speed.  Inlining the call (TRUE) typically increases the
50 *  size of RTEMS while speeding up the enabling of dispatching.
51 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
52 *  only be 0 or 1 unless you are in an interrupt handler and that
53 *  interrupt handler invokes the executive.]  When not inlined
54 *  something calls _Thread_Enable_dispatch which in turns calls
55 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
56 *  one subroutine call is avoided entirely.]
57 */
58
59#define CPU_INLINE_ENABLE_DISPATCH       FALSE
60
61/*
62 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
63 *  be unrolled one time?  In unrolled each iteration of the loop examines
64 *  two "nodes" on the chain being searched.  Otherwise, only one node
65 *  is examined per iteration.
66 *
67 *  If TRUE, then the loops are unrolled.
68 *  If FALSE, then the loops are not unrolled.
69 *
70 *  The primary factor in making this decision is the cost of disabling
71 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
72 *  body of the loop.  On some CPUs, the flash is more expensive than
73 *  one iteration of the loop body.  In this case, it might be desirable
74 *  to unroll the loop.  It is important to note that on some CPUs, this
75 *  code is the longest interrupt disable period in RTEMS.  So it is
76 *  necessary to strike a balance when setting this parameter.
77 */
78
79#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
80
81/*
82 *  Does RTEMS manage a dedicated interrupt stack in software?
83 *
84 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
85 *  If FALSE, nothing is done.
86 *
87 *  If the CPU supports a dedicated interrupt stack in hardware,
88 *  then it is generally the responsibility of the BSP to allocate it
89 *  and set it up.
90 *
91 *  If the CPU does not support a dedicated interrupt stack, then
92 *  the porter has two options: (1) execute interrupts on the
93 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
94 *  interrupt stack.
95 *
96 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
97 *
98 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
99 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
100 *  possible that both are FALSE for a particular CPU.  Although it
101 *  is unclear what that would imply about the interrupt processing
102 *  procedure on that CPU.
103 */
104
105#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
106#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
107
108/*
109 * We define the interrupt stack in the linker script
110 */
111#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
112
113/*
114 *  Does the RTEMS invoke the user's ISR with the vector number and
115 *  a pointer to the saved interrupt frame (1) or just the vector
116 *  number (0)?
117 */
118
119#define CPU_ISR_PASSES_FRAME_POINTER 0
120
121/*
122 *  Does the CPU have hardware floating point?
123 *
124 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
125 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
126 *
127 *  We currently support sh1 only, which has no FPU, other SHes have an FPU
128 *
129 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
130 *  It indicates whether or not this CPU model has FP support.  For
131 *  example, it would be possible to have an i386_nofp CPU model
132 *  which set this to false to indicate that you have an i386 without
133 *  an i387 and wish to leave floating point support out of RTEMS.
134 */
135
136#if SH_HAS_FPU
137#define CPU_HARDWARE_FP TRUE
138#define CPU_SOFTWARE_FP FALSE
139#else
140#define CPU_SOFTWARE_FP FALSE
141#define CPU_HARDWARE_FP FALSE
142#endif
143
144/*
145 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
146 *
147 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
148 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
149 *
150 *  So far, the only CPU in which this option has been used is the
151 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
152 *  floating point registers to perform integer multiplies.  If
153 *  a function which you would not think utilize the FP unit DOES,
154 *  then one can not easily predict which tasks will use the FP hardware.
155 *  In this case, this option should be TRUE.
156 *
157 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
158 */
159
160#if SH_HAS_FPU
161#define CPU_ALL_TASKS_ARE_FP     TRUE
162#else
163#define CPU_ALL_TASKS_ARE_FP     FALSE
164#endif
165
166/*
167 *  Should the IDLE task have a floating point context?
168 *
169 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
170 *  and it has a floating point context which is switched in and out.
171 *  If FALSE, then the IDLE task does not have a floating point context.
172 *
173 *  Setting this to TRUE negatively impacts the time required to preempt
174 *  the IDLE task from an interrupt because the floating point context
175 *  must be saved as part of the preemption.
176 */
177
178#if SH_HAS_FPU
179#define CPU_IDLE_TASK_IS_FP     TRUE
180#else
181#define CPU_IDLE_TASK_IS_FP      FALSE
182#endif
183
184/*
185 *  Should the saving of the floating point registers be deferred
186 *  until a context switch is made to another different floating point
187 *  task?
188 *
189 *  If TRUE, then the floating point context will not be stored until
190 *  necessary.  It will remain in the floating point registers and not
191 *  disturned until another floating point task is switched to.
192 *
193 *  If FALSE, then the floating point context is saved when a floating
194 *  point task is switched out and restored when the next floating point
195 *  task is restored.  The state of the floating point registers between
196 *  those two operations is not specified.
197 *
198 *  If the floating point context does NOT have to be saved as part of
199 *  interrupt dispatching, then it should be safe to set this to TRUE.
200 *
201 *  Setting this flag to TRUE results in using a different algorithm
202 *  for deciding when to save and restore the floating point context.
203 *  The deferred FP switch algorithm minimizes the number of times
204 *  the FP context is saved and restored.  The FP context is not saved
205 *  until a context switch is made to another, different FP task.
206 *  Thus in a system with only one FP task, the FP context will never
207 *  be saved or restored.
208 */
209
210#if SH_HAS_FPU
211#define CPU_USE_DEFERRED_FP_SWITCH      FALSE
212#else
213#define CPU_USE_DEFERRED_FP_SWITCH      TRUE
214#endif
215
216/*
217 *  Does this port provide a CPU dependent IDLE task implementation?
218 *
219 *  If TRUE, then the routine _CPU_Thread_Idle_body
220 *  must be provided and is the default IDLE thread body instead of
221 *  _CPU_Thread_Idle_body.
222 *
223 *  If FALSE, then use the generic IDLE thread body if the BSP does
224 *  not provide one.
225 *
226 *  This is intended to allow for supporting processors which have
227 *  a low power or idle mode.  When the IDLE thread is executed, then
228 *  the CPU can be powered down.
229 *
230 *  The order of precedence for selecting the IDLE thread body is:
231 *
232 *    1.  BSP provided
233 *    2.  CPU dependent (if provided)
234 *    3.  generic (if no BSP and no CPU dependent)
235 */
236
237#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
238
239/*
240 *  Does the stack grow up (toward higher addresses) or down
241 *  (toward lower addresses)?
242 *
243 *  If TRUE, then the grows upward.
244 *  If FALSE, then the grows toward smaller addresses.
245 */
246
247#define CPU_STACK_GROWS_UP               FALSE
248
249/*
250 *  The following is the variable attribute used to force alignment
251 *  of critical RTEMS structures.  On some processors it may make
252 *  sense to have these aligned on tighter boundaries than
253 *  the minimum requirements of the compiler in order to have as
254 *  much of the critical data area as possible in a cache line.
255 *
256 *  The placement of this macro in the declaration of the variables
257 *  is based on the syntactically requirements of the GNU C
258 *  "__attribute__" extension.  For example with GNU C, use
259 *  the following to force a structures to a 32 byte boundary.
260 *
261 *      __attribute__ ((aligned (32)))
262 *
263 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
264 *         To benefit from using this, the data must be heavily
265 *         used so it will stay in the cache and used frequently enough
266 *         in the executive to justify turning this on.
267 */
268
269#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned(16)))
270
271/*
272 *  Define what is required to specify how the network to host conversion
273 *  routines are handled.
274 *
275 *  NOTE: SHes can be big or little endian, the default is big endian
276 */
277
278#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
279
280/* __LITTLE_ENDIAN__ is defined if -ml is given to gcc */
281#if defined(__LITTLE_ENDIAN__)
282#define CPU_BIG_ENDIAN                           FALSE
283#define CPU_LITTLE_ENDIAN                        TRUE
284#else
285#define CPU_BIG_ENDIAN                           TRUE
286#define CPU_LITTLE_ENDIAN                        FALSE
287#endif
288 
289/*
290 *  The following defines the number of bits actually used in the
291 *  interrupt field of the task mode.  How those bits map to the
292 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
293 */
294
295#define CPU_MODES_INTERRUPT_MASK   0x0000000f
296
297/*
298 *  Processor defined structures
299 *
300 *  Examples structures include the descriptor tables from the i386
301 *  and the processor control structure on the i960ca.
302 */
303
304/* may need to put some structures here.  */
305
306/*
307 * Contexts
308 *
309 *  Generally there are 2 types of context to save.
310 *     1. Interrupt registers to save
311 *     2. Task level registers to save
312 *
313 *  This means we have the following 3 context items:
314 *     1. task level context stuff::  Context_Control
315 *     2. floating point task stuff:: Context_Control_fp
316 *     3. special interrupt level context :: Context_Control_interrupt
317 *
318 *  On some processors, it is cost-effective to save only the callee
319 *  preserved registers during a task context switch.  This means
320 *  that the ISR code needs to save those registers which do not
321 *  persist across function calls.  It is not mandatory to make this
322 *  distinctions between the caller/callee saves registers for the
323 *  purpose of minimizing context saved during task switch and on interrupts.
324 *  If the cost of saving extra registers is minimal, simplicity is the
325 *  choice.  Save the same context on interrupt entry as for tasks in
326 *  this case.
327 *
328 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
329 *  care should be used in designing the context area.
330 *
331 *  On some CPUs with hardware floating point support, the Context_Control_fp
332 *  structure will not be used or it simply consist of an array of a
333 *  fixed number of bytes.   This is done when the floating point context
334 *  is dumped by a "FP save context" type instruction and the format
335 *  is not really defined by the CPU.  In this case, there is no need
336 *  to figure out the exact format -- only the size.  Of course, although
337 *  this is enough information for RTEMS, it is probably not enough for
338 *  a debugger such as gdb.  But that is another problem.
339 */
340
341typedef struct {
342  unsigned32 *r15;      /* stack pointer */
343
344  unsigned32 macl;
345  unsigned32 mach;
346  unsigned32 *pr;
347
348  unsigned32 *r14;      /* frame pointer/call saved */
349
350  unsigned32 r13;       /* call saved */
351  unsigned32 r12;       /* call saved */
352  unsigned32 r11;       /* call saved */
353  unsigned32 r10;       /* call saved */
354  unsigned32 r9;        /* call saved */
355  unsigned32 r8;        /* call saved */
356
357  unsigned32 *r7;       /* arg in */
358  unsigned32 *r6;       /* arg in */
359
360#if 0
361  unsigned32 *r5;       /* arg in */
362  unsigned32 *r4;       /* arg in */
363#endif
364
365  unsigned32 *r3;       /* scratch */
366  unsigned32 *r2;       /* scratch */
367  unsigned32 *r1;       /* scratch */
368
369  unsigned32 *r0;       /* arg return */
370
371  unsigned32 gbr;
372  unsigned32 sr; 
373
374} Context_Control;
375
376typedef struct {
377#if SH_HAS_FPU
378#ifdef SH4_USE_X_REGISTERS
379  union {
380    float f[16];
381    double d[8];
382  } x;
383#endif
384  union {
385    float f[16];
386    double d[8];
387  } r;
388  float fpul;       /* fp communication register */
389  unsigned32 fpscr; /* fp control register */
390#endif /* SH_HAS_FPU */
391} Context_Control_fp;
392
393typedef struct {
394} CPU_Interrupt_frame;
395
396
397/*
398 *  The following table contains the information required to configure
399 *  the SH processor specific parameters.
400 */
401
402typedef struct {
403  void       (*pretasking_hook)( void );
404  void       (*predriver_hook)( void );
405  void       (*postdriver_hook)( void );
406  void       (*idle_task)( void );
407  boolean      do_zero_of_workspace;
408  unsigned32   idle_task_stack_size;
409  unsigned32   interrupt_stack_size;
410  unsigned32   extra_mpci_receive_server_stack;
411  void *     (*stack_allocate_hook)( unsigned32 );
412  void       (*stack_free_hook)( void* );
413  /* end of fields required on all CPUs */
414  unsigned32    clicks_per_second ; /* cpu frequency in Hz */
415}   rtems_cpu_table;
416
417/*
418 *  Macros to access required entires in the CPU Table are in
419 *  the file rtems/system.h.
420 */
421
422/*
423 *  Macros to access SH specific additions to the CPU Table
424 */
425
426#define rtems_cpu_configuration_get_clicks_per_second() \
427  (_CPU_Table.clicks_per_second)
428   
429/*
430 *  This variable is optional.  It is used on CPUs on which it is difficult
431 *  to generate an "uninitialized" FP context.  It is filled in by
432 *  _CPU_Initialize and copied into the task's FP context area during
433 *  _CPU_Context_Initialize.
434 */
435
436#if SH_HAS_FPU
437SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
438#endif
439
440/*
441 *  On some CPUs, RTEMS supports a software managed interrupt stack.
442 *  This stack is allocated by the Interrupt Manager and the switch
443 *  is performed in _ISR_Handler.  These variables contain pointers
444 *  to the lowest and highest addresses in the chunk of memory allocated
445 *  for the interrupt stack.  Since it is unknown whether the stack
446 *  grows up or down (in general), this give the CPU dependent
447 *  code the option of picking the version it wants to use.
448 *
449 *  NOTE: These two variables are required if the macro
450 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
451 */
452
453SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
454SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
455
456/*
457 *  With some compilation systems, it is difficult if not impossible to
458 *  call a high-level language routine from assembly language.  This
459 *  is especially true of commercial Ada compilers and name mangling
460 *  C++ ones.  This variable can be optionally defined by the CPU porter
461 *  and contains the address of the routine _Thread_Dispatch.  This
462 *  can make it easier to invoke that routine at the end of the interrupt
463 *  sequence (if a dispatch is necessary).
464 */
465
466SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
467
468/*
469 *  Nothing prevents the porter from declaring more CPU specific variables.
470 */
471
472/* XXX: if needed, put more variables here */
473SCORE_EXTERN void CPU_delay( unsigned32 microseconds );
474
475/*
476 *  The size of the floating point context area.  On some CPUs this
477 *  will not be a "sizeof" because the format of the floating point
478 *  area is not defined -- only the size is.  This is usually on
479 *  CPUs with a "floating point save context" instruction.
480 */
481
482#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
483
484/*
485 *  Amount of extra stack (above minimum stack size) required by
486 *  MPCI receive server thread.  Remember that in a multiprocessor
487 *  system this thread must exist and be able to process all directives.
488 */
489
490#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
491
492/*
493 *  This defines the number of entries in the ISR_Vector_table managed
494 *  by RTEMS.
495 */
496
497#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
498#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
499
500/*
501 *  This is defined if the port has a special way to report the ISR nesting
502 *  level.  Most ports maintain the variable _ISR_Nest_level.
503 */
504
505#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
506
507/*
508 *  Should be large enough to run all RTEMS tests.  This insures
509 *  that a "reasonable" small application should not have any problems.
510 *
511 *  We have been able to run the sptests with this value, but have not
512 *  been able to run the tmtest suite.
513 */
514
515#define CPU_STACK_MINIMUM_SIZE          4096
516
517/*
518 *  CPU's worst alignment requirement for data types on a byte boundary.  This
519 *  alignment does not take into account the requirements for the stack.
520 */
521#if defined(__SH4__)
522/* FIXME: sh3 and SH3E? */
523#define CPU_ALIGNMENT              8
524#else
525#define CPU_ALIGNMENT              4
526#endif
527
528/*
529 *  This number corresponds to the byte alignment requirement for the
530 *  heap handler.  This alignment requirement may be stricter than that
531 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
532 *  common for the heap to follow the same alignment requirement as
533 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
534 *  then this should be set to CPU_ALIGNMENT.
535 *
536 *  NOTE:  This does not have to be a power of 2.  It does have to
537 *         be greater or equal to than CPU_ALIGNMENT.
538 */
539
540#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
541
542/*
543 *  This number corresponds to the byte alignment requirement for memory
544 *  buffers allocated by the partition manager.  This alignment requirement
545 *  may be stricter than that for the data types alignment specified by
546 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
547 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
548 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
549 *
550 *  NOTE:  This does not have to be a power of 2.  It does have to
551 *         be greater or equal to than CPU_ALIGNMENT.
552 */
553
554#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
555
556/*
557 *  This number corresponds to the byte alignment requirement for the
558 *  stack.  This alignment requirement may be stricter than that for the
559 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
560 *  is strict enough for the stack, then this should be set to 0.
561 *
562 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
563 */
564
565#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
566
567/*
568 *  ISR handler macros
569 */
570
571/*
572 *  Support routine to initialize the RTEMS vector table after it is allocated.
573 *
574 *  SH Specific Information: NONE
575 */
576 
577#define _CPU_Initialize_vectors()
578 
579/*
580 *  Disable all interrupts for an RTEMS critical section.  The previous
581 *  level is returned in _level.
582 */
583
584#define _CPU_ISR_Disable( _level) \
585  sh_disable_interrupts( _level )
586
587/*
588 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
589 *  This indicates the end of an RTEMS critical section.  The parameter
590 *  _level is not modified.
591 */
592
593#define _CPU_ISR_Enable( _level) \
594   sh_enable_interrupts( _level)
595
596/*
597 *  This temporarily restores the interrupt to _level before immediately
598 *  disabling them again.  This is used to divide long RTEMS critical
599 *  sections into two or more parts.  The parameter _level is not
600 * modified.
601 */
602
603#define _CPU_ISR_Flash( _level) \
604  sh_flash_interrupts( _level)
605
606/*
607 *  Map interrupt level in task mode onto the hardware that the CPU
608 *  actually provides.  Currently, interrupt levels which do not
609 *  map onto the CPU in a generic fashion are undefined.  Someday,
610 *  it would be nice if these were "mapped" by the application
611 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
612 *  8 - 255 would be available for bsp/application specific meaning.
613 *  This could be used to manage a programmable interrupt controller
614 *  via the rtems_task_mode directive.
615 */
616
617#define _CPU_ISR_Set_level( _newlevel) \
618  sh_set_interrupt_level(_newlevel)
619
620unsigned32 _CPU_ISR_Get_level( void );
621
622/* end of ISR handler macros */
623
624/* Context handler macros */
625
626/*
627 *  Initialize the context to a state suitable for starting a
628 *  task after a context restore operation.  Generally, this
629 *  involves:
630 *
631 *     - setting a starting address
632 *     - preparing the stack
633 *     - preparing the stack and frame pointers
634 *     - setting the proper interrupt level in the context
635 *     - initializing the floating point context
636 *
637 *  This routine generally does not set any unnecessary register
638 *  in the context.  The state of the "general data" registers is
639 *  undefined at task start time.
640 *
641 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
642 *        point thread.  This is typically only used on CPUs where the
643 *        FPU may be easily disabled by software such as on the SPARC
644 *        where the PSR contains an enable FPU bit.
645 */
646
647/*
648 * FIXME: defined as a function for debugging - should be a macro
649 */
650SCORE_EXTERN void _CPU_Context_Initialize(
651  Context_Control       *_the_context,
652  void                  *_stack_base,
653  unsigned32            _size,
654  unsigned32            _isr,
655  void    (*_entry_point)(void),
656  int                   _is_fp );
657
658/*
659 *  This routine is responsible for somehow restarting the currently
660 *  executing task.  If you are lucky, then all that is necessary
661 *  is restoring the context.  Otherwise, there will need to be
662 *  a special assembly routine which does something special in this
663 *  case.  Context_Restore should work most of the time.  It will
664 *  not work if restarting self conflicts with the stack frame
665 *  assumptions of restoring a context.
666 */
667
668#define _CPU_Context_Restart_self( _the_context ) \
669   _CPU_Context_restore( (_the_context) );
670
671/*
672 *  The purpose of this macro is to allow the initial pointer into
673 *  a floating point context area (used to save the floating point
674 *  context) to be at an arbitrary place in the floating point
675 *  context area.
676 *
677 *  This is necessary because some FP units are designed to have
678 *  their context saved as a stack which grows into lower addresses.
679 *  Other FP units can be saved by simply moving registers into offsets
680 *  from the base of the context area.  Finally some FP units provide
681 *  a "dump context" instruction which could fill in from high to low
682 *  or low to high based on the whim of the CPU designers.
683 */
684
685#define _CPU_Context_Fp_start( _base, _offset ) \
686   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
687
688/*
689 *  This routine initializes the FP context area passed to it to.
690 *  There are a few standard ways in which to initialize the
691 *  floating point context.  The code included for this macro assumes
692 *  that this is a CPU in which a "initial" FP context was saved into
693 *  _CPU_Null_fp_context and it simply copies it to the destination
694 *  context passed to it.
695 *
696 *  Other models include (1) not doing anything, and (2) putting
697 *  a "null FP status word" in the correct place in the FP context.
698 *  SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have.
699 */
700
701#if SH_HAS_FPU
702#define _CPU_Context_Initialize_fp( _destination ) \
703  do { \
704     *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\
705  } while(0)
706#else
707#define _CPU_Context_Initialize_fp( _destination ) \
708  {  }
709#endif
710
711/* end of Context handler macros */
712
713/* Fatal Error manager macros */
714
715/*
716 * FIXME: Trap32 ???
717 *
718 *  This routine copies _error into a known place -- typically a stack
719 *  location or a register, optionally disables interrupts, and
720 *  invokes a Trap32 Instruction which returns to the breakpoint
721 *  routine of cmon.
722 */
723
724#ifdef BSP_FATAL_HALT
725  /* we manage the fatal error in the board support package */
726  void bsp_fatal_halt( unsigned32 _error);
727#define _CPU_Fatal_halt( _error ) bsp_fatal_halt( _error)
728#else
729#define _CPU_Fatal_halt( _error)\
730{ \
731  asm volatile("mov.l %0,r0"::"m" (_error)); \
732  asm volatile("mov #1, r4"); \
733  asm volatile("trapa #34"); \
734}
735#endif
736
737/* end of Fatal Error manager macros */
738
739/* Bitfield handler macros */
740
741/*
742 *  This routine sets _output to the bit number of the first bit
743 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
744 *  This type may be either 16 or 32 bits wide although only the 16
745 *  least significant bits will be used.
746 *
747 *  There are a number of variables in using a "find first bit" type
748 *  instruction.
749 *
750 *    (1) What happens when run on a value of zero?
751 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
752 *    (3) The numbering may be zero or one based.
753 *    (4) The "find first bit" instruction may search from MSB or LSB.
754 *
755 *  RTEMS guarantees that (1) will never happen so it is not a concern.
756 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
757 *  _CPU_Priority_bits_index().  These three form a set of routines
758 *  which must logically operate together.  Bits in the _value are
759 *  set and cleared based on masks built by _CPU_Priority_mask().
760 *  The basic major and minor values calculated by _Priority_Major()
761 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
762 *  to properly range between the values returned by the "find first bit"
763 *  instruction.  This makes it possible for _Priority_Get_highest() to
764 *  calculate the major and directly index into the minor table.
765 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
766 *  is the first bit found.
767 *
768 *  This entire "find first bit" and mapping process depends heavily
769 *  on the manner in which a priority is broken into a major and minor
770 *  components with the major being the 4 MSB of a priority and minor
771 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
772 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
773 *  to the lowest priority.
774 *
775 *  If your CPU does not have a "find first bit" instruction, then
776 *  there are ways to make do without it.  Here are a handful of ways
777 *  to implement this in software:
778 *
779 *    - a series of 16 bit test instructions
780 *    - a "binary search using if's"
781 *    - _number = 0
782 *      if _value > 0x00ff
783 *        _value >>=8
784 *        _number = 8;
785 *
786 *      if _value > 0x0000f
787 *        _value >=8
788 *        _number += 4
789 *
790 *      _number += bit_set_table[ _value ]
791 *
792 *    where bit_set_table[ 16 ] has values which indicate the first
793 *      bit set
794 */
795
796#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
797#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
798
799#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
800
801extern unsigned8 _bit_set_table[];
802
803#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
804  { \
805      _output = 0;\
806      if(_value > 0x00ff) \
807      { _value >>= 8; _output = 8; } \
808      if(_value > 0x000f) \
809        { _output += 4; _value >>= 4; } \
810      _output += _bit_set_table[ _value]; }
811
812#endif
813
814/* end of Bitfield handler macros */
815
816/*
817 *  This routine builds the mask which corresponds to the bit fields
818 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
819 *  for that routine.
820 */
821
822#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
823
824#define _CPU_Priority_Mask( _bit_number ) \
825  ( 1 << (_bit_number) )
826
827#endif
828
829/*
830 *  This routine translates the bit numbers returned by
831 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
832 *  a major or minor component of a priority.  See the discussion
833 *  for that routine.
834 */
835
836#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
837
838#define _CPU_Priority_bits_index( _priority ) \
839  (_priority)
840
841#endif
842
843/* end of Priority handler macros */
844
845/* functions */
846
847/*
848 *  _CPU_Initialize
849 *
850 *  This routine performs CPU dependent initialization.
851 */
852
853void _CPU_Initialize(
854  rtems_cpu_table  *cpu_table,
855  void      (*thread_dispatch)
856);
857
858/*
859 *  _CPU_ISR_install_raw_handler
860 *
861 *  This routine installs a "raw" interrupt handler directly into the
862 *  processor's vector table.
863 */
864 
865void _CPU_ISR_install_raw_handler(
866  unsigned32  vector,
867  proc_ptr    new_handler,
868  proc_ptr   *old_handler
869);
870
871/*
872 *  _CPU_ISR_install_vector
873 *
874 *  This routine installs an interrupt vector.
875 */
876
877void _CPU_ISR_install_vector(
878  unsigned32  vector,
879  proc_ptr    new_handler,
880  proc_ptr   *old_handler
881);
882
883/*
884 *  _CPU_Install_interrupt_stack
885 *
886 *  This routine installs the hardware interrupt stack pointer.
887 *
888 *  NOTE:  It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
889 *         is TRUE.
890 */
891
892void _CPU_Install_interrupt_stack( void );
893
894/*
895 *  _CPU_Thread_Idle_body
896 *
897 *  This routine is the CPU dependent IDLE thread body.
898 *
899 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
900 *         is TRUE.
901 */
902
903void _CPU_Thread_Idle_body( void );
904
905/*
906 *  _CPU_Context_switch
907 *
908 *  This routine switches from the run context to the heir context.
909 */
910
911void _CPU_Context_switch(
912  Context_Control  *run,
913  Context_Control  *heir
914);
915
916/*
917 *  _CPU_Context_restore
918 *
919 *  This routine is generally used only to restart self in an
920 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
921 */
922
923void _CPU_Context_restore(
924  Context_Control *new_context
925);
926
927/*
928 *  _CPU_Context_save_fp
929 *
930 *  This routine saves the floating point context passed to it.
931 */
932
933void _CPU_Context_save_fp(
934  void **fp_context_ptr
935);
936
937/*
938 *  _CPU_Context_restore_fp
939 *
940 *  This routine restores the floating point context passed to it.
941 */
942
943void _CPU_Context_restore_fp(
944  void **fp_context_ptr
945);
946
947
948#ifdef __cplusplus
949}
950#endif
951
952#endif
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