source: rtems/cpukit/score/cpu/sh/rtems/score/cpu.h @ 4ef13360

4.11
Last change on this file since 4ef13360 was 4ef13360, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 29, 2010 at 5:51:56 PM

2010-07-29 Gedare Bloom <giddyup44@…>

PR 1635/cpukit

  • rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority handling, to isolate the bitmap implementation of priorities in the supercore so that priority management is a little more modular. This change is in anticipation of scheduler implementations that can select how they manage tracking priority levels / finding the highest priority ready task. Note that most of the changes here are simple renaming, to clarify the use of the bitmap-based priority management.
  • Property mode set to 100644
File size: 26.9 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the Hitachi SH
7 *  processor.
8 *
9 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
10 *           Bernd Becker (becker@faw.uni-ulm.de)
11 *
12 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
13 *
14 *  This program is distributed in the hope that it will be useful,
15 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 *
18 *
19 *  COPYRIGHT (c) 1998-2006.
20 *  On-Line Applications Research Corporation (OAR).
21 *
22 *  The license and distribution terms for this file may be
23 *  found in the file LICENSE in this distribution or at
24 *  http://www.rtems.com/license/LICENSE.
25 *
26 *  $Id$
27 */
28
29#ifndef _RTEMS_SCORE_CPU_H
30#define _RTEMS_SCORE_CPU_H
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
36#include <rtems/score/types.h>
37#include <rtems/score/sh.h>
38
39/* conditional compilation parameters */
40
41/*
42 *  Should the calls to _Thread_Enable_dispatch be inlined?
43 *
44 *  If TRUE, then they are inlined.
45 *  If FALSE, then a subroutine call is made.
46 *
47 *  Basically this is an example of the classic trade-off of size
48 *  versus speed.  Inlining the call (TRUE) typically increases the
49 *  size of RTEMS while speeding up the enabling of dispatching.
50 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
51 *  only be 0 or 1 unless you are in an interrupt handler and that
52 *  interrupt handler invokes the executive.]  When not inlined
53 *  something calls _Thread_Enable_dispatch which in turns calls
54 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
55 *  one subroutine call is avoided entirely.]
56 */
57
58#define CPU_INLINE_ENABLE_DISPATCH       FALSE
59
60/*
61 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
62 *  be unrolled one time?  In unrolled each iteration of the loop examines
63 *  two "nodes" on the chain being searched.  Otherwise, only one node
64 *  is examined per iteration.
65 *
66 *  If TRUE, then the loops are unrolled.
67 *  If FALSE, then the loops are not unrolled.
68 *
69 *  The primary factor in making this decision is the cost of disabling
70 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
71 *  body of the loop.  On some CPUs, the flash is more expensive than
72 *  one iteration of the loop body.  In this case, it might be desirable
73 *  to unroll the loop.  It is important to note that on some CPUs, this
74 *  code is the longest interrupt disable period in RTEMS.  So it is
75 *  necessary to strike a balance when setting this parameter.
76 */
77
78#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
79
80/*
81 *  Does the CPU follow the simple vectored interrupt model?
82 *
83 *  If TRUE, then RTEMS allocates the vector table it internally manages.
84 *  If FALSE, then the BSP is assumed to allocate and manage the vector
85 *  table
86 *
87 *  SH Specific Information:
88 *
89 *  XXX document implementation including references if appropriate
90 */
91#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
92
93/*
94 *  Does RTEMS manage a dedicated interrupt stack in software?
95 *
96 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
97 *  If FALSE, nothing is done.
98 *
99 *  If the CPU supports a dedicated interrupt stack in hardware,
100 *  then it is generally the responsibility of the BSP to allocate it
101 *  and set it up.
102 *
103 *  If the CPU does not support a dedicated interrupt stack, then
104 *  the porter has two options: (1) execute interrupts on the
105 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
106 *  interrupt stack.
107 *
108 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
109 *
110 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
111 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
112 *  possible that both are FALSE for a particular CPU.  Although it
113 *  is unclear what that would imply about the interrupt processing
114 *  procedure on that CPU.
115 */
116
117#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
118#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
119
120/*
121 * We define the interrupt stack in the linker script
122 */
123#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
124
125/*
126 *  Does the RTEMS invoke the user's ISR with the vector number and
127 *  a pointer to the saved interrupt frame (1) or just the vector
128 *  number (0)?
129 */
130
131#define CPU_ISR_PASSES_FRAME_POINTER 0
132
133/*
134 *  Does the CPU have hardware floating point?
135 *
136 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
137 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
138 *
139 *  We currently support sh1 only, which has no FPU, other SHes have an FPU
140 *
141 *  The macro name "SH_HAS_FPU" should be made CPU specific.
142 *  It indicates whether or not this CPU model has FP support.  For
143 *  example, it would be possible to have an i386_nofp CPU model
144 *  which set this to false to indicate that you have an i386 without
145 *  an i387 and wish to leave floating point support out of RTEMS.
146 */
147
148#if SH_HAS_FPU
149#define CPU_HARDWARE_FP TRUE
150#define CPU_SOFTWARE_FP FALSE
151#else
152#define CPU_SOFTWARE_FP FALSE
153#define CPU_HARDWARE_FP FALSE
154#endif
155
156/*
157 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
158 *
159 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
160 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
161 *
162 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
163 */
164
165#if SH_HAS_FPU
166#define CPU_ALL_TASKS_ARE_FP     TRUE
167#else
168#define CPU_ALL_TASKS_ARE_FP     FALSE
169#endif
170
171/*
172 *  Should the IDLE task have a floating point context?
173 *
174 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
175 *  and it has a floating point context which is switched in and out.
176 *  If FALSE, then the IDLE task does not have a floating point context.
177 *
178 *  Setting this to TRUE negatively impacts the time required to preempt
179 *  the IDLE task from an interrupt because the floating point context
180 *  must be saved as part of the preemption.
181 */
182
183#if SH_HAS_FPU
184#define CPU_IDLE_TASK_IS_FP     TRUE
185#else
186#define CPU_IDLE_TASK_IS_FP      FALSE
187#endif
188
189/*
190 *  Should the saving of the floating point registers be deferred
191 *  until a context switch is made to another different floating point
192 *  task?
193 *
194 *  If TRUE, then the floating point context will not be stored until
195 *  necessary.  It will remain in the floating point registers and not
196 *  disturned until another floating point task is switched to.
197 *
198 *  If FALSE, then the floating point context is saved when a floating
199 *  point task is switched out and restored when the next floating point
200 *  task is restored.  The state of the floating point registers between
201 *  those two operations is not specified.
202 *
203 *  If the floating point context does NOT have to be saved as part of
204 *  interrupt dispatching, then it should be safe to set this to TRUE.
205 *
206 *  Setting this flag to TRUE results in using a different algorithm
207 *  for deciding when to save and restore the floating point context.
208 *  The deferred FP switch algorithm minimizes the number of times
209 *  the FP context is saved and restored.  The FP context is not saved
210 *  until a context switch is made to another, different FP task.
211 *  Thus in a system with only one FP task, the FP context will never
212 *  be saved or restored.
213 */
214
215#if SH_HAS_FPU
216#define CPU_USE_DEFERRED_FP_SWITCH      FALSE
217#else
218#define CPU_USE_DEFERRED_FP_SWITCH      TRUE
219#endif
220
221/*
222 *  Does this port provide a CPU dependent IDLE task implementation?
223 *
224 *  If TRUE, then the routine _CPU_Thread_Idle_body
225 *  must be provided and is the default IDLE thread body instead of
226 *  _CPU_Thread_Idle_body.
227 *
228 *  If FALSE, then use the generic IDLE thread body if the BSP does
229 *  not provide one.
230 *
231 *  This is intended to allow for supporting processors which have
232 *  a low power or idle mode.  When the IDLE thread is executed, then
233 *  the CPU can be powered down.
234 *
235 *  The order of precedence for selecting the IDLE thread body is:
236 *
237 *    1.  BSP provided
238 *    2.  CPU dependent (if provided)
239 *    3.  generic (if no BSP and no CPU dependent)
240 */
241
242#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
243
244/*
245 *  Does the stack grow up (toward higher addresses) or down
246 *  (toward lower addresses)?
247 *
248 *  If TRUE, then the grows upward.
249 *  If FALSE, then the grows toward smaller addresses.
250 */
251
252#define CPU_STACK_GROWS_UP               FALSE
253
254/*
255 *  The following is the variable attribute used to force alignment
256 *  of critical RTEMS structures.  On some processors it may make
257 *  sense to have these aligned on tighter boundaries than
258 *  the minimum requirements of the compiler in order to have as
259 *  much of the critical data area as possible in a cache line.
260 *
261 *  The placement of this macro in the declaration of the variables
262 *  is based on the syntactically requirements of the GNU C
263 *  "__attribute__" extension.  For example with GNU C, use
264 *  the following to force a structures to a 32 byte boundary.
265 *
266 *      __attribute__ ((aligned (32)))
267 *
268 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
269 *         To benefit from using this, the data must be heavily
270 *         used so it will stay in the cache and used frequently enough
271 *         in the executive to justify turning this on.
272 */
273
274#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned(16)))
275
276/*
277 *  Define what is required to specify how the network to host conversion
278 *  routines are handled.
279 *
280 *  NOTE: SHes can be big or little endian, the default is big endian
281 */
282
283/* __LITTLE_ENDIAN__ is defined if -ml is given to gcc */
284#if defined(__LITTLE_ENDIAN__)
285#define CPU_BIG_ENDIAN                           FALSE
286#define CPU_LITTLE_ENDIAN                        TRUE
287#else
288#define CPU_BIG_ENDIAN                           TRUE
289#define CPU_LITTLE_ENDIAN                        FALSE
290#endif
291
292/*
293 *  The following defines the number of bits actually used in the
294 *  interrupt field of the task mode.  How those bits map to the
295 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
296 */
297
298#define CPU_MODES_INTERRUPT_MASK   0x0000000f
299
300/*
301 *  Processor defined structures required for cpukit/score.
302 */
303
304/* may need to put some structures here.  */
305
306/*
307 * Contexts
308 *
309 *  Generally there are 2 types of context to save.
310 *     1. Interrupt registers to save
311 *     2. Task level registers to save
312 *
313 *  This means we have the following 3 context items:
314 *     1. task level context stuff::  Context_Control
315 *     2. floating point task stuff:: Context_Control_fp
316 *     3. special interrupt level context :: Context_Control_interrupt
317 *
318 *  On some processors, it is cost-effective to save only the callee
319 *  preserved registers during a task context switch.  This means
320 *  that the ISR code needs to save those registers which do not
321 *  persist across function calls.  It is not mandatory to make this
322 *  distinctions between the caller/callee saves registers for the
323 *  purpose of minimizing context saved during task switch and on interrupts.
324 *  If the cost of saving extra registers is minimal, simplicity is the
325 *  choice.  Save the same context on interrupt entry as for tasks in
326 *  this case.
327 *
328 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
329 *  care should be used in designing the context area.
330 *
331 *  On some CPUs with hardware floating point support, the Context_Control_fp
332 *  structure will not be used or it simply consist of an array of a
333 *  fixed number of bytes.   This is done when the floating point context
334 *  is dumped by a "FP save context" type instruction and the format
335 *  is not really defined by the CPU.  In this case, there is no need
336 *  to figure out the exact format -- only the size.  Of course, although
337 *  this is enough information for RTEMS, it is probably not enough for
338 *  a debugger such as gdb.  But that is another problem.
339 */
340
341typedef struct {
342  uint32_t   *r15;      /* stack pointer */
343
344  uint32_t   macl;
345  uint32_t   mach;
346  uint32_t   *pr;
347
348  uint32_t   *r14;      /* frame pointer/call saved */
349
350  uint32_t   r13;       /* call saved */
351  uint32_t   r12;       /* call saved */
352  uint32_t   r11;       /* call saved */
353  uint32_t   r10;       /* call saved */
354  uint32_t   r9;        /* call saved */
355  uint32_t   r8;        /* call saved */
356
357  uint32_t   *r7;       /* arg in */
358  uint32_t   *r6;       /* arg in */
359
360#if 0
361  uint32_t   *r5;       /* arg in */
362  uint32_t   *r4;       /* arg in */
363#endif
364
365  uint32_t   *r3;       /* scratch */
366  uint32_t   *r2;       /* scratch */
367  uint32_t   *r1;       /* scratch */
368
369  uint32_t   *r0;       /* arg return */
370
371  uint32_t   gbr;
372  uint32_t   sr;
373
374} Context_Control;
375
376#define _CPU_Context_Get_SP( _context ) \
377  (_context)->r15
378
379typedef struct {
380#if SH_HAS_FPU
381#ifdef SH4_USE_X_REGISTERS
382  union {
383    float f[16];
384    double d[8];
385  } x;
386#endif
387  union {
388    float f[16];
389    double d[8];
390  } r;
391  float fpul;       /* fp communication register */
392  uint32_t   fpscr; /* fp control register */
393#endif /* SH_HAS_FPU */
394} Context_Control_fp;
395
396typedef struct {
397} CPU_Interrupt_frame;
398
399/*
400 *  This variable is optional.  It is used on CPUs on which it is difficult
401 *  to generate an "uninitialized" FP context.  It is filled in by
402 *  _CPU_Initialize and copied into the task's FP context area during
403 *  _CPU_Context_Initialize.
404 */
405
406#if SH_HAS_FPU
407SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
408#endif
409
410/*
411 *  Nothing prevents the porter from declaring more CPU specific variables.
412 */
413
414/* XXX: if needed, put more variables here */
415SCORE_EXTERN void CPU_delay( uint32_t   microseconds );
416
417/*
418 *  The size of the floating point context area.  On some CPUs this
419 *  will not be a "sizeof" because the format of the floating point
420 *  area is not defined -- only the size is.  This is usually on
421 *  CPUs with a "floating point save context" instruction.
422 */
423
424#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
425
426/*
427 *  Amount of extra stack (above minimum stack size) required by
428 *  MPCI receive server thread.  Remember that in a multiprocessor
429 *  system this thread must exist and be able to process all directives.
430 */
431
432#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
433
434/*
435 *  This defines the number of entries in the ISR_Vector_table managed
436 *  by RTEMS.
437 */
438
439#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
440#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
441
442/*
443 *  This is defined if the port has a special way to report the ISR nesting
444 *  level.  Most ports maintain the variable _ISR_Nest_level.
445 */
446
447#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
448
449/*
450 *  Should be large enough to run all RTEMS tests.  This ensures
451 *  that a "reasonable" small application should not have any problems.
452 *
453 *  We have been able to run the sptests with this value, but have not
454 *  been able to run the tmtest suite.
455 */
456
457#define CPU_STACK_MINIMUM_SIZE          4096
458
459/*
460 *  CPU's worst alignment requirement for data types on a byte boundary.  This
461 *  alignment does not take into account the requirements for the stack.
462 */
463#if defined(__SH4__)
464/* FIXME: sh3 and SH3E? */
465#define CPU_ALIGNMENT              8
466#else
467#define CPU_ALIGNMENT              4
468#endif
469
470/*
471 *  This number corresponds to the byte alignment requirement for the
472 *  heap handler.  This alignment requirement may be stricter than that
473 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
474 *  common for the heap to follow the same alignment requirement as
475 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
476 *  then this should be set to CPU_ALIGNMENT.
477 *
478 *  NOTE:  This does not have to be a power of 2.  It does have to
479 *         be greater or equal to than CPU_ALIGNMENT.
480 */
481
482#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
483
484/*
485 *  This number corresponds to the byte alignment requirement for memory
486 *  buffers allocated by the partition manager.  This alignment requirement
487 *  may be stricter than that for the data types alignment specified by
488 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
489 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
490 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
491 *
492 *  NOTE:  This does not have to be a power of 2.  It does have to
493 *         be greater or equal to than CPU_ALIGNMENT.
494 */
495
496#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
497
498/*
499 *  This number corresponds to the byte alignment requirement for the
500 *  stack.  This alignment requirement may be stricter than that for the
501 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
502 *  is strict enough for the stack, then this should be set to 0.
503 *
504 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
505 */
506
507#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
508
509/*
510 *  ISR handler macros
511 */
512
513/*
514 *  Support routine to initialize the RTEMS vector table after it is allocated.
515 *
516 *  SH Specific Information: NONE
517 */
518
519#define _CPU_Initialize_vectors()
520
521/*
522 *  Disable all interrupts for an RTEMS critical section.  The previous
523 *  level is returned in _level.
524 */
525
526#define _CPU_ISR_Disable( _level) \
527  sh_disable_interrupts( _level )
528
529/*
530 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
531 *  This indicates the end of an RTEMS critical section.  The parameter
532 *  _level is not modified.
533 */
534
535#define _CPU_ISR_Enable( _level) \
536   sh_enable_interrupts( _level)
537
538/*
539 *  This temporarily restores the interrupt to _level before immediately
540 *  disabling them again.  This is used to divide long RTEMS critical
541 *  sections into two or more parts.  The parameter _level is not
542 * modified.
543 */
544
545#define _CPU_ISR_Flash( _level) \
546  sh_flash_interrupts( _level)
547
548/*
549 *  Map interrupt level in task mode onto the hardware that the CPU
550 *  actually provides.  Currently, interrupt levels which do not
551 *  map onto the CPU in a generic fashion are undefined.  Someday,
552 *  it would be nice if these were "mapped" by the application
553 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
554 *  8 - 255 would be available for bsp/application specific meaning.
555 *  This could be used to manage a programmable interrupt controller
556 *  via the rtems_task_mode directive.
557 */
558
559#define _CPU_ISR_Set_level( _newlevel) \
560  sh_set_interrupt_level(_newlevel)
561
562uint32_t   _CPU_ISR_Get_level( void );
563
564/* end of ISR handler macros */
565
566/* Context handler macros */
567
568/*
569 *  Initialize the context to a state suitable for starting a
570 *  task after a context restore operation.  Generally, this
571 *  involves:
572 *
573 *     - setting a starting address
574 *     - preparing the stack
575 *     - preparing the stack and frame pointers
576 *     - setting the proper interrupt level in the context
577 *     - initializing the floating point context
578 *
579 *  This routine generally does not set any unnecessary register
580 *  in the context.  The state of the "general data" registers is
581 *  undefined at task start time.
582 *
583 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
584 *        point thread.  This is typically only used on CPUs where the
585 *        FPU may be easily disabled by software such as on the SPARC
586 *        where the PSR contains an enable FPU bit.
587 */
588
589/*
590 * FIXME: defined as a function for debugging - should be a macro
591 */
592SCORE_EXTERN void _CPU_Context_Initialize(
593  Context_Control       *_the_context,
594  void                  *_stack_base,
595  uint32_t              _size,
596  uint32_t              _isr,
597  void    (*_entry_point)(void),
598  int                   _is_fp );
599
600/*
601 *  This routine is responsible for somehow restarting the currently
602 *  executing task.  If you are lucky, then all that is necessary
603 *  is restoring the context.  Otherwise, there will need to be
604 *  a special assembly routine which does something special in this
605 *  case.  Context_Restore should work most of the time.  It will
606 *  not work if restarting self conflicts with the stack frame
607 *  assumptions of restoring a context.
608 */
609
610#define _CPU_Context_Restart_self( _the_context ) \
611   _CPU_Context_restore( (_the_context) );
612
613/*
614 *  The purpose of this macro is to allow the initial pointer into
615 *  a floating point context area (used to save the floating point
616 *  context) to be at an arbitrary place in the floating point
617 *  context area.
618 *
619 *  This is necessary because some FP units are designed to have
620 *  their context saved as a stack which grows into lower addresses.
621 *  Other FP units can be saved by simply moving registers into offsets
622 *  from the base of the context area.  Finally some FP units provide
623 *  a "dump context" instruction which could fill in from high to low
624 *  or low to high based on the whim of the CPU designers.
625 */
626
627#define _CPU_Context_Fp_start( _base, _offset ) \
628   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
629
630/*
631 *  This routine initializes the FP context area passed to it to.
632 *  There are a few standard ways in which to initialize the
633 *  floating point context.  The code included for this macro assumes
634 *  that this is a CPU in which a "initial" FP context was saved into
635 *  _CPU_Null_fp_context and it simply copies it to the destination
636 *  context passed to it.
637 *
638 *  Other models include (1) not doing anything, and (2) putting
639 *  a "null FP status word" in the correct place in the FP context.
640 *  SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have.
641 */
642
643#if SH_HAS_FPU
644#define _CPU_Context_Initialize_fp( _destination ) \
645  do { \
646     *(*(_destination)) = _CPU_Null_fp_context;\
647  } while(0)
648#else
649#define _CPU_Context_Initialize_fp( _destination ) \
650  {  }
651#endif
652
653/* end of Context handler macros */
654
655/* Fatal Error manager macros */
656
657/*
658 * FIXME: Trap32 ???
659 *
660 *  This routine copies _error into a known place -- typically a stack
661 *  location or a register, optionally disables interrupts, and
662 *  invokes a Trap32 Instruction which returns to the breakpoint
663 *  routine of cmon.
664 */
665
666#ifdef BSP_FATAL_HALT
667  /* we manage the fatal error in the board support package */
668  void bsp_fatal_halt( uint32_t   _error);
669#define _CPU_Fatal_halt( _error ) bsp_fatal_halt( _error)
670#else
671#define _CPU_Fatal_halt( _error)\
672{ \
673  asm volatile("mov.l %0,r0"::"m" (_error)); \
674  asm volatile("mov #1, r4"); \
675  asm volatile("trapa #34"); \
676}
677#endif
678
679/* end of Fatal Error manager macros */
680
681/* Bitfield handler macros */
682
683/*
684 *  This routine sets _output to the bit number of the first bit
685 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Control.
686 *  This type may be either 16 or 32 bits wide although only the 16
687 *  least significant bits will be used.
688 *
689 *  There are a number of variables in using a "find first bit" type
690 *  instruction.
691 *
692 *    (1) What happens when run on a value of zero?
693 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
694 *    (3) The numbering may be zero or one based.
695 *    (4) The "find first bit" instruction may search from MSB or LSB.
696 *
697 *  RTEMS guarantees that (1) will never happen so it is not a concern.
698 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
699 *  _CPU_Priority_bits_index().  These three form a set of routines
700 *  which must logically operate together.  Bits in the _value are
701 *  set and cleared based on masks built by _CPU_Priority_mask().
702 *  The basic major and minor values calculated by _Priority_Major()
703 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
704 *  to properly range between the values returned by the "find first bit"
705 *  instruction.  This makes it possible for _Priority_Get_highest() to
706 *  calculate the major and directly index into the minor table.
707 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
708 *  is the first bit found.
709 *
710 *  This entire "find first bit" and mapping process depends heavily
711 *  on the manner in which a priority is broken into a major and minor
712 *  components with the major being the 4 MSB of a priority and minor
713 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
714 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
715 *  to the lowest priority.
716 *
717 *  If your CPU does not have a "find first bit" instruction, then
718 *  there are ways to make do without it.  Here are a handful of ways
719 *  to implement this in software:
720 *
721 *    - a series of 16 bit test instructions
722 *    - a "binary search using if's"
723 *    - _number = 0
724 *      if _value > 0x00ff
725 *        _value >>=8
726 *        _number = 8;
727 *
728 *      if _value > 0x0000f
729 *        _value >=8
730 *        _number += 4
731 *
732 *      _number += bit_set_table[ _value ]
733 *
734 *    where bit_set_table[ 16 ] has values which indicate the first
735 *      bit set
736 */
737
738#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
739#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
740
741#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
742
743extern uint8_t   _bit_set_table[];
744
745#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
746  { \
747      _output = 0;\
748      if(_value > 0x00ff) \
749      { _value >>= 8; _output = 8; } \
750      if(_value > 0x000f) \
751        { _output += 4; _value >>= 4; } \
752      _output += _bit_set_table[ _value]; }
753
754#endif
755
756/* end of Bitfield handler macros */
757
758/*
759 *  This routine builds the mask which corresponds to the bit fields
760 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
761 *  for that routine.
762 */
763
764#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
765
766#define _CPU_Priority_Mask( _bit_number ) \
767  ( 1 << (_bit_number) )
768
769#endif
770
771/*
772 *  This routine translates the bit numbers returned by
773 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
774 *  a major or minor component of a priority.  See the discussion
775 *  for that routine.
776 */
777
778#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
779
780#define _CPU_Priority_bits_index( _priority ) \
781  (_priority)
782
783#endif
784
785/* end of Priority handler macros */
786
787/* functions */
788
789/*
790 *  _CPU_Initialize
791 *
792 *  This routine performs CPU dependent initialization.
793 */
794
795void _CPU_Initialize(void);
796
797/*
798 *  _CPU_ISR_install_raw_handler
799 *
800 *  This routine installs a "raw" interrupt handler directly into the
801 *  processor's vector table.
802 */
803
804void _CPU_ISR_install_raw_handler(
805  uint32_t    vector,
806  proc_ptr    new_handler,
807  proc_ptr   *old_handler
808);
809
810/*
811 *  _CPU_ISR_install_vector
812 *
813 *  This routine installs an interrupt vector.
814 */
815
816void _CPU_ISR_install_vector(
817  uint32_t    vector,
818  proc_ptr    new_handler,
819  proc_ptr   *old_handler
820);
821
822/*
823 *  _CPU_Install_interrupt_stack
824 *
825 *  This routine installs the hardware interrupt stack pointer.
826 *
827 *  NOTE:  It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
828 *         is TRUE.
829 */
830
831void _CPU_Install_interrupt_stack( void );
832
833/*
834 *  _CPU_Thread_Idle_body
835 *
836 *  This routine is the CPU dependent IDLE thread body.
837 *
838 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
839 *         is TRUE.
840 */
841
842void *_CPU_Thread_Idle_body( uintptr_t ignored );
843
844/*
845 *  _CPU_Context_switch
846 *
847 *  This routine switches from the run context to the heir context.
848 */
849
850void _CPU_Context_switch(
851  Context_Control  *run,
852  Context_Control  *heir
853);
854
855/*
856 *  _CPU_Context_restore
857 *
858 *  This routine is generally used only to restart self in an
859 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
860 */
861
862void _CPU_Context_restore(
863  Context_Control *new_context
864);
865
866/*
867 *  _CPU_Context_save_fp
868 *
869 *  This routine saves the floating point context passed to it.
870 */
871
872void _CPU_Context_save_fp(
873  Context_Control_fp **fp_context_ptr
874);
875
876/*
877 *  _CPU_Context_restore_fp
878 *
879 *  This routine restores the floating point context passed to it.
880 */
881
882void _CPU_Context_restore_fp(
883  Context_Control_fp **fp_context_ptr
884);
885
886
887#ifdef __cplusplus
888}
889#endif
890
891#endif
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