source: rtems/cpukit/score/cpu/sh/rtems/score/cpu.h @ 3c87adba

4.104.114.9
Last change on this file since 3c87adba was 3c87adba, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 31, 2008 at 2:55:56 PM

2008-07-31 Joel Sherrill <joel.sherrill@…>

  • cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads.
  • Property mode set to 100644
File size: 28.3 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the Hitachi SH
7 *  processor.
8 *
9 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
10 *           Bernd Becker (becker@faw.uni-ulm.de)
11 *
12 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
13 *
14 *  This program is distributed in the hope that it will be useful,
15 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 *
18 *
19 *  COPYRIGHT (c) 1998-2006.
20 *  On-Line Applications Research Corporation (OAR).
21 *
22 *  The license and distribution terms for this file may be
23 *  found in the file LICENSE in this distribution or at
24 *  http://www.rtems.com/license/LICENSE.
25 *
26 *  $Id$
27 */
28
29#ifndef _RTEMS_SCORE_CPU_H
30#define _RTEMS_SCORE_CPU_H
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
36#include <rtems/score/sh.h>              /* pick up machine definitions */
37#ifndef ASM
38#include <rtems/score/types.h>
39#endif
40#if 0 && defined(__SH4__)
41#include <rtems/score/sh4_regs.h>
42#endif
43
44/* conditional compilation parameters */
45
46/*
47 *  Should the calls to _Thread_Enable_dispatch be inlined?
48 *
49 *  If TRUE, then they are inlined.
50 *  If FALSE, then a subroutine call is made.
51 *
52 *  Basically this is an example of the classic trade-off of size
53 *  versus speed.  Inlining the call (TRUE) typically increases the
54 *  size of RTEMS while speeding up the enabling of dispatching.
55 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
56 *  only be 0 or 1 unless you are in an interrupt handler and that
57 *  interrupt handler invokes the executive.]  When not inlined
58 *  something calls _Thread_Enable_dispatch which in turns calls
59 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
60 *  one subroutine call is avoided entirely.]
61 */
62
63#define CPU_INLINE_ENABLE_DISPATCH       FALSE
64
65/*
66 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
67 *  be unrolled one time?  In unrolled each iteration of the loop examines
68 *  two "nodes" on the chain being searched.  Otherwise, only one node
69 *  is examined per iteration.
70 *
71 *  If TRUE, then the loops are unrolled.
72 *  If FALSE, then the loops are not unrolled.
73 *
74 *  The primary factor in making this decision is the cost of disabling
75 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
76 *  body of the loop.  On some CPUs, the flash is more expensive than
77 *  one iteration of the loop body.  In this case, it might be desirable
78 *  to unroll the loop.  It is important to note that on some CPUs, this
79 *  code is the longest interrupt disable period in RTEMS.  So it is
80 *  necessary to strike a balance when setting this parameter.
81 */
82
83#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
84
85/*
86 *  Does the CPU follow the simple vectored interrupt model?
87 *
88 *  If TRUE, then RTEMS allocates the vector table it internally manages.
89 *  If FALSE, then the BSP is assumed to allocate and manage the vector
90 *  table
91 *
92 *  SH Specific Information:
93 *
94 *  XXX document implementation including references if appropriate
95 */
96#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
97
98/*
99 *  Does RTEMS manage a dedicated interrupt stack in software?
100 *
101 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
102 *  If FALSE, nothing is done.
103 *
104 *  If the CPU supports a dedicated interrupt stack in hardware,
105 *  then it is generally the responsibility of the BSP to allocate it
106 *  and set it up.
107 *
108 *  If the CPU does not support a dedicated interrupt stack, then
109 *  the porter has two options: (1) execute interrupts on the
110 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
111 *  interrupt stack.
112 *
113 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
114 *
115 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
116 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
117 *  possible that both are FALSE for a particular CPU.  Although it
118 *  is unclear what that would imply about the interrupt processing
119 *  procedure on that CPU.
120 */
121
122#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
123#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
124
125/*
126 * We define the interrupt stack in the linker script
127 */
128#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
129
130/*
131 *  Does the RTEMS invoke the user's ISR with the vector number and
132 *  a pointer to the saved interrupt frame (1) or just the vector
133 *  number (0)?
134 */
135
136#define CPU_ISR_PASSES_FRAME_POINTER 0
137
138/*
139 *  Does the CPU have hardware floating point?
140 *
141 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
142 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
143 *
144 *  We currently support sh1 only, which has no FPU, other SHes have an FPU
145 *
146 *  The macro name "SH_HAS_FPU" should be made CPU specific.
147 *  It indicates whether or not this CPU model has FP support.  For
148 *  example, it would be possible to have an i386_nofp CPU model
149 *  which set this to false to indicate that you have an i386 without
150 *  an i387 and wish to leave floating point support out of RTEMS.
151 */
152
153#if SH_HAS_FPU
154#define CPU_HARDWARE_FP TRUE
155#define CPU_SOFTWARE_FP FALSE
156#else
157#define CPU_SOFTWARE_FP FALSE
158#define CPU_HARDWARE_FP FALSE
159#endif
160
161/*
162 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
163 *
164 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
165 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
166 *
167 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
168 */
169
170#if SH_HAS_FPU
171#define CPU_ALL_TASKS_ARE_FP     TRUE
172#else
173#define CPU_ALL_TASKS_ARE_FP     FALSE
174#endif
175
176/*
177 *  Should the IDLE task have a floating point context?
178 *
179 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
180 *  and it has a floating point context which is switched in and out.
181 *  If FALSE, then the IDLE task does not have a floating point context.
182 *
183 *  Setting this to TRUE negatively impacts the time required to preempt
184 *  the IDLE task from an interrupt because the floating point context
185 *  must be saved as part of the preemption.
186 */
187
188#if SH_HAS_FPU
189#define CPU_IDLE_TASK_IS_FP     TRUE
190#else
191#define CPU_IDLE_TASK_IS_FP      FALSE
192#endif
193
194/*
195 *  Should the saving of the floating point registers be deferred
196 *  until a context switch is made to another different floating point
197 *  task?
198 *
199 *  If TRUE, then the floating point context will not be stored until
200 *  necessary.  It will remain in the floating point registers and not
201 *  disturned until another floating point task is switched to.
202 *
203 *  If FALSE, then the floating point context is saved when a floating
204 *  point task is switched out and restored when the next floating point
205 *  task is restored.  The state of the floating point registers between
206 *  those two operations is not specified.
207 *
208 *  If the floating point context does NOT have to be saved as part of
209 *  interrupt dispatching, then it should be safe to set this to TRUE.
210 *
211 *  Setting this flag to TRUE results in using a different algorithm
212 *  for deciding when to save and restore the floating point context.
213 *  The deferred FP switch algorithm minimizes the number of times
214 *  the FP context is saved and restored.  The FP context is not saved
215 *  until a context switch is made to another, different FP task.
216 *  Thus in a system with only one FP task, the FP context will never
217 *  be saved or restored.
218 */
219
220#if SH_HAS_FPU
221#define CPU_USE_DEFERRED_FP_SWITCH      FALSE
222#else
223#define CPU_USE_DEFERRED_FP_SWITCH      TRUE
224#endif
225
226/*
227 *  Does this port provide a CPU dependent IDLE task implementation?
228 *
229 *  If TRUE, then the routine _CPU_Thread_Idle_body
230 *  must be provided and is the default IDLE thread body instead of
231 *  _CPU_Thread_Idle_body.
232 *
233 *  If FALSE, then use the generic IDLE thread body if the BSP does
234 *  not provide one.
235 *
236 *  This is intended to allow for supporting processors which have
237 *  a low power or idle mode.  When the IDLE thread is executed, then
238 *  the CPU can be powered down.
239 *
240 *  The order of precedence for selecting the IDLE thread body is:
241 *
242 *    1.  BSP provided
243 *    2.  CPU dependent (if provided)
244 *    3.  generic (if no BSP and no CPU dependent)
245 */
246
247#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
248
249/*
250 *  Does the stack grow up (toward higher addresses) or down
251 *  (toward lower addresses)?
252 *
253 *  If TRUE, then the grows upward.
254 *  If FALSE, then the grows toward smaller addresses.
255 */
256
257#define CPU_STACK_GROWS_UP               FALSE
258
259/*
260 *  The following is the variable attribute used to force alignment
261 *  of critical RTEMS structures.  On some processors it may make
262 *  sense to have these aligned on tighter boundaries than
263 *  the minimum requirements of the compiler in order to have as
264 *  much of the critical data area as possible in a cache line.
265 *
266 *  The placement of this macro in the declaration of the variables
267 *  is based on the syntactically requirements of the GNU C
268 *  "__attribute__" extension.  For example with GNU C, use
269 *  the following to force a structures to a 32 byte boundary.
270 *
271 *      __attribute__ ((aligned (32)))
272 *
273 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
274 *         To benefit from using this, the data must be heavily
275 *         used so it will stay in the cache and used frequently enough
276 *         in the executive to justify turning this on.
277 */
278
279#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned(16)))
280
281/*
282 *  Define what is required to specify how the network to host conversion
283 *  routines are handled.
284 *
285 *  NOTE: SHes can be big or little endian, the default is big endian
286 */
287
288/* __LITTLE_ENDIAN__ is defined if -ml is given to gcc */
289#if defined(__LITTLE_ENDIAN__)
290#define CPU_BIG_ENDIAN                           FALSE
291#define CPU_LITTLE_ENDIAN                        TRUE
292#else
293#define CPU_BIG_ENDIAN                           TRUE
294#define CPU_LITTLE_ENDIAN                        FALSE
295#endif
296 
297/*
298 *  The following defines the number of bits actually used in the
299 *  interrupt field of the task mode.  How those bits map to the
300 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
301 */
302
303#define CPU_MODES_INTERRUPT_MASK   0x0000000f
304
305/*
306 *  Processor defined structures required for cpukit/score.
307 */
308
309/* may need to put some structures here.  */
310
311/*
312 * Contexts
313 *
314 *  Generally there are 2 types of context to save.
315 *     1. Interrupt registers to save
316 *     2. Task level registers to save
317 *
318 *  This means we have the following 3 context items:
319 *     1. task level context stuff::  Context_Control
320 *     2. floating point task stuff:: Context_Control_fp
321 *     3. special interrupt level context :: Context_Control_interrupt
322 *
323 *  On some processors, it is cost-effective to save only the callee
324 *  preserved registers during a task context switch.  This means
325 *  that the ISR code needs to save those registers which do not
326 *  persist across function calls.  It is not mandatory to make this
327 *  distinctions between the caller/callee saves registers for the
328 *  purpose of minimizing context saved during task switch and on interrupts.
329 *  If the cost of saving extra registers is minimal, simplicity is the
330 *  choice.  Save the same context on interrupt entry as for tasks in
331 *  this case.
332 *
333 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
334 *  care should be used in designing the context area.
335 *
336 *  On some CPUs with hardware floating point support, the Context_Control_fp
337 *  structure will not be used or it simply consist of an array of a
338 *  fixed number of bytes.   This is done when the floating point context
339 *  is dumped by a "FP save context" type instruction and the format
340 *  is not really defined by the CPU.  In this case, there is no need
341 *  to figure out the exact format -- only the size.  Of course, although
342 *  this is enough information for RTEMS, it is probably not enough for
343 *  a debugger such as gdb.  But that is another problem.
344 */
345
346typedef struct {
347  uint32_t   *r15;      /* stack pointer */
348
349  uint32_t   macl;
350  uint32_t   mach;
351  uint32_t   *pr;
352
353  uint32_t   *r14;      /* frame pointer/call saved */
354
355  uint32_t   r13;       /* call saved */
356  uint32_t   r12;       /* call saved */
357  uint32_t   r11;       /* call saved */
358  uint32_t   r10;       /* call saved */
359  uint32_t   r9;        /* call saved */
360  uint32_t   r8;        /* call saved */
361
362  uint32_t   *r7;       /* arg in */
363  uint32_t   *r6;       /* arg in */
364
365#if 0
366  uint32_t   *r5;       /* arg in */
367  uint32_t   *r4;       /* arg in */
368#endif
369
370  uint32_t   *r3;       /* scratch */
371  uint32_t   *r2;       /* scratch */
372  uint32_t   *r1;       /* scratch */
373
374  uint32_t   *r0;       /* arg return */
375
376  uint32_t   gbr;
377  uint32_t   sr; 
378
379} Context_Control;
380
381#define _CPU_Context_Get_SP( _context ) \
382  (_context)->r15
383
384typedef struct {
385#if SH_HAS_FPU
386#ifdef SH4_USE_X_REGISTERS
387  union {
388    float f[16];
389    double d[8];
390  } x;
391#endif
392  union {
393    float f[16];
394    double d[8];
395  } r;
396  float fpul;       /* fp communication register */
397  uint32_t   fpscr; /* fp control register */
398#endif /* SH_HAS_FPU */
399} Context_Control_fp;
400
401typedef struct {
402} CPU_Interrupt_frame;
403
404/*
405 *  This variable is optional.  It is used on CPUs on which it is difficult
406 *  to generate an "uninitialized" FP context.  It is filled in by
407 *  _CPU_Initialize and copied into the task's FP context area during
408 *  _CPU_Context_Initialize.
409 */
410
411#if SH_HAS_FPU
412SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
413#endif
414
415/*
416 *  On some CPUs, RTEMS supports a software managed interrupt stack.
417 *  This stack is allocated by the Interrupt Manager and the switch
418 *  is performed in _ISR_Handler.  These variables contain pointers
419 *  to the lowest and highest addresses in the chunk of memory allocated
420 *  for the interrupt stack.  Since it is unknown whether the stack
421 *  grows up or down (in general), this give the CPU dependent
422 *  code the option of picking the version it wants to use.
423 *
424 *  NOTE: These two variables are required if the macro
425 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
426 */
427
428SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
429SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
430
431/*
432 *  With some compilation systems, it is difficult if not impossible to
433 *  call a high-level language routine from assembly language.  This
434 *  is especially true of commercial Ada compilers and name mangling
435 *  C++ ones.  This variable can be optionally defined by the CPU porter
436 *  and contains the address of the routine _Thread_Dispatch.  This
437 *  can make it easier to invoke that routine at the end of the interrupt
438 *  sequence (if a dispatch is necessary).
439 */
440
441SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
442
443/*
444 *  Nothing prevents the porter from declaring more CPU specific variables.
445 */
446
447/* XXX: if needed, put more variables here */
448SCORE_EXTERN void CPU_delay( uint32_t   microseconds );
449
450/*
451 *  The size of the floating point context area.  On some CPUs this
452 *  will not be a "sizeof" because the format of the floating point
453 *  area is not defined -- only the size is.  This is usually on
454 *  CPUs with a "floating point save context" instruction.
455 */
456
457#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
458
459/*
460 *  Amount of extra stack (above minimum stack size) required by
461 *  MPCI receive server thread.  Remember that in a multiprocessor
462 *  system this thread must exist and be able to process all directives.
463 */
464
465#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
466
467/*
468 *  This defines the number of entries in the ISR_Vector_table managed
469 *  by RTEMS.
470 */
471
472#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
473#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
474
475/*
476 *  This is defined if the port has a special way to report the ISR nesting
477 *  level.  Most ports maintain the variable _ISR_Nest_level.
478 */
479
480#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
481
482/*
483 *  Should be large enough to run all RTEMS tests.  This ensures
484 *  that a "reasonable" small application should not have any problems.
485 *
486 *  We have been able to run the sptests with this value, but have not
487 *  been able to run the tmtest suite.
488 */
489
490#define CPU_STACK_MINIMUM_SIZE          4096
491
492/*
493 *  CPU's worst alignment requirement for data types on a byte boundary.  This
494 *  alignment does not take into account the requirements for the stack.
495 */
496#if defined(__SH4__)
497/* FIXME: sh3 and SH3E? */
498#define CPU_ALIGNMENT              8
499#else
500#define CPU_ALIGNMENT              4
501#endif
502
503/*
504 *  This number corresponds to the byte alignment requirement for the
505 *  heap handler.  This alignment requirement may be stricter than that
506 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
507 *  common for the heap to follow the same alignment requirement as
508 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
509 *  then this should be set to CPU_ALIGNMENT.
510 *
511 *  NOTE:  This does not have to be a power of 2.  It does have to
512 *         be greater or equal to than CPU_ALIGNMENT.
513 */
514
515#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
516
517/*
518 *  This number corresponds to the byte alignment requirement for memory
519 *  buffers allocated by the partition manager.  This alignment requirement
520 *  may be stricter than that for the data types alignment specified by
521 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
522 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
523 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
524 *
525 *  NOTE:  This does not have to be a power of 2.  It does have to
526 *         be greater or equal to than CPU_ALIGNMENT.
527 */
528
529#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
530
531/*
532 *  This number corresponds to the byte alignment requirement for the
533 *  stack.  This alignment requirement may be stricter than that for the
534 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
535 *  is strict enough for the stack, then this should be set to 0.
536 *
537 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
538 */
539
540#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
541
542/*
543 *  ISR handler macros
544 */
545
546/*
547 *  Support routine to initialize the RTEMS vector table after it is allocated.
548 *
549 *  SH Specific Information: NONE
550 */
551 
552#define _CPU_Initialize_vectors()
553 
554/*
555 *  Disable all interrupts for an RTEMS critical section.  The previous
556 *  level is returned in _level.
557 */
558
559#define _CPU_ISR_Disable( _level) \
560  sh_disable_interrupts( _level )
561
562/*
563 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
564 *  This indicates the end of an RTEMS critical section.  The parameter
565 *  _level is not modified.
566 */
567
568#define _CPU_ISR_Enable( _level) \
569   sh_enable_interrupts( _level)
570
571/*
572 *  This temporarily restores the interrupt to _level before immediately
573 *  disabling them again.  This is used to divide long RTEMS critical
574 *  sections into two or more parts.  The parameter _level is not
575 * modified.
576 */
577
578#define _CPU_ISR_Flash( _level) \
579  sh_flash_interrupts( _level)
580
581/*
582 *  Map interrupt level in task mode onto the hardware that the CPU
583 *  actually provides.  Currently, interrupt levels which do not
584 *  map onto the CPU in a generic fashion are undefined.  Someday,
585 *  it would be nice if these were "mapped" by the application
586 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
587 *  8 - 255 would be available for bsp/application specific meaning.
588 *  This could be used to manage a programmable interrupt controller
589 *  via the rtems_task_mode directive.
590 */
591
592#define _CPU_ISR_Set_level( _newlevel) \
593  sh_set_interrupt_level(_newlevel)
594
595uint32_t   _CPU_ISR_Get_level( void );
596
597/* end of ISR handler macros */
598
599/* Context handler macros */
600
601/*
602 *  Initialize the context to a state suitable for starting a
603 *  task after a context restore operation.  Generally, this
604 *  involves:
605 *
606 *     - setting a starting address
607 *     - preparing the stack
608 *     - preparing the stack and frame pointers
609 *     - setting the proper interrupt level in the context
610 *     - initializing the floating point context
611 *
612 *  This routine generally does not set any unnecessary register
613 *  in the context.  The state of the "general data" registers is
614 *  undefined at task start time.
615 *
616 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
617 *        point thread.  This is typically only used on CPUs where the
618 *        FPU may be easily disabled by software such as on the SPARC
619 *        where the PSR contains an enable FPU bit.
620 */
621
622/*
623 * FIXME: defined as a function for debugging - should be a macro
624 */
625SCORE_EXTERN void _CPU_Context_Initialize(
626  Context_Control       *_the_context,
627  void                  *_stack_base,
628  uint32_t              _size,
629  uint32_t              _isr,
630  void    (*_entry_point)(void),
631  int                   _is_fp );
632
633/*
634 *  This routine is responsible for somehow restarting the currently
635 *  executing task.  If you are lucky, then all that is necessary
636 *  is restoring the context.  Otherwise, there will need to be
637 *  a special assembly routine which does something special in this
638 *  case.  Context_Restore should work most of the time.  It will
639 *  not work if restarting self conflicts with the stack frame
640 *  assumptions of restoring a context.
641 */
642
643#define _CPU_Context_Restart_self( _the_context ) \
644   _CPU_Context_restore( (_the_context) );
645
646/*
647 *  The purpose of this macro is to allow the initial pointer into
648 *  a floating point context area (used to save the floating point
649 *  context) to be at an arbitrary place in the floating point
650 *  context area.
651 *
652 *  This is necessary because some FP units are designed to have
653 *  their context saved as a stack which grows into lower addresses.
654 *  Other FP units can be saved by simply moving registers into offsets
655 *  from the base of the context area.  Finally some FP units provide
656 *  a "dump context" instruction which could fill in from high to low
657 *  or low to high based on the whim of the CPU designers.
658 */
659
660#define _CPU_Context_Fp_start( _base, _offset ) \
661   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
662
663/*
664 *  This routine initializes the FP context area passed to it to.
665 *  There are a few standard ways in which to initialize the
666 *  floating point context.  The code included for this macro assumes
667 *  that this is a CPU in which a "initial" FP context was saved into
668 *  _CPU_Null_fp_context and it simply copies it to the destination
669 *  context passed to it.
670 *
671 *  Other models include (1) not doing anything, and (2) putting
672 *  a "null FP status word" in the correct place in the FP context.
673 *  SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have.
674 */
675
676#if SH_HAS_FPU
677#define _CPU_Context_Initialize_fp( _destination ) \
678  do { \
679     *(*(_destination)) = _CPU_Null_fp_context;\
680  } while(0)
681#else
682#define _CPU_Context_Initialize_fp( _destination ) \
683  {  }
684#endif
685
686/* end of Context handler macros */
687
688/* Fatal Error manager macros */
689
690/*
691 * FIXME: Trap32 ???
692 *
693 *  This routine copies _error into a known place -- typically a stack
694 *  location or a register, optionally disables interrupts, and
695 *  invokes a Trap32 Instruction which returns to the breakpoint
696 *  routine of cmon.
697 */
698
699#ifdef BSP_FATAL_HALT
700  /* we manage the fatal error in the board support package */
701  void bsp_fatal_halt( uint32_t   _error);
702#define _CPU_Fatal_halt( _error ) bsp_fatal_halt( _error)
703#else
704#define _CPU_Fatal_halt( _error)\
705{ \
706  asm volatile("mov.l %0,r0"::"m" (_error)); \
707  asm volatile("mov #1, r4"); \
708  asm volatile("trapa #34"); \
709}
710#endif
711
712/* end of Fatal Error manager macros */
713
714/* Bitfield handler macros */
715
716/*
717 *  This routine sets _output to the bit number of the first bit
718 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
719 *  This type may be either 16 or 32 bits wide although only the 16
720 *  least significant bits will be used.
721 *
722 *  There are a number of variables in using a "find first bit" type
723 *  instruction.
724 *
725 *    (1) What happens when run on a value of zero?
726 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
727 *    (3) The numbering may be zero or one based.
728 *    (4) The "find first bit" instruction may search from MSB or LSB.
729 *
730 *  RTEMS guarantees that (1) will never happen so it is not a concern.
731 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
732 *  _CPU_Priority_bits_index().  These three form a set of routines
733 *  which must logically operate together.  Bits in the _value are
734 *  set and cleared based on masks built by _CPU_Priority_mask().
735 *  The basic major and minor values calculated by _Priority_Major()
736 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
737 *  to properly range between the values returned by the "find first bit"
738 *  instruction.  This makes it possible for _Priority_Get_highest() to
739 *  calculate the major and directly index into the minor table.
740 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
741 *  is the first bit found.
742 *
743 *  This entire "find first bit" and mapping process depends heavily
744 *  on the manner in which a priority is broken into a major and minor
745 *  components with the major being the 4 MSB of a priority and minor
746 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
747 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
748 *  to the lowest priority.
749 *
750 *  If your CPU does not have a "find first bit" instruction, then
751 *  there are ways to make do without it.  Here are a handful of ways
752 *  to implement this in software:
753 *
754 *    - a series of 16 bit test instructions
755 *    - a "binary search using if's"
756 *    - _number = 0
757 *      if _value > 0x00ff
758 *        _value >>=8
759 *        _number = 8;
760 *
761 *      if _value > 0x0000f
762 *        _value >=8
763 *        _number += 4
764 *
765 *      _number += bit_set_table[ _value ]
766 *
767 *    where bit_set_table[ 16 ] has values which indicate the first
768 *      bit set
769 */
770
771#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
772#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
773
774#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
775
776extern uint8_t   _bit_set_table[];
777
778#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
779  { \
780      _output = 0;\
781      if(_value > 0x00ff) \
782      { _value >>= 8; _output = 8; } \
783      if(_value > 0x000f) \
784        { _output += 4; _value >>= 4; } \
785      _output += _bit_set_table[ _value]; }
786
787#endif
788
789/* end of Bitfield handler macros */
790
791/*
792 *  This routine builds the mask which corresponds to the bit fields
793 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
794 *  for that routine.
795 */
796
797#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
798
799#define _CPU_Priority_Mask( _bit_number ) \
800  ( 1 << (_bit_number) )
801
802#endif
803
804/*
805 *  This routine translates the bit numbers returned by
806 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
807 *  a major or minor component of a priority.  See the discussion
808 *  for that routine.
809 */
810
811#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
812
813#define _CPU_Priority_bits_index( _priority ) \
814  (_priority)
815
816#endif
817
818/* end of Priority handler macros */
819
820/* functions */
821
822/*
823 *  _CPU_Initialize
824 *
825 *  This routine performs CPU dependent initialization.
826 */
827
828void _CPU_Initialize(
829  void      (*thread_dispatch)
830);
831
832/*
833 *  _CPU_ISR_install_raw_handler
834 *
835 *  This routine installs a "raw" interrupt handler directly into the
836 *  processor's vector table.
837 */
838 
839void _CPU_ISR_install_raw_handler(
840  uint32_t    vector,
841  proc_ptr    new_handler,
842  proc_ptr   *old_handler
843);
844
845/*
846 *  _CPU_ISR_install_vector
847 *
848 *  This routine installs an interrupt vector.
849 */
850
851void _CPU_ISR_install_vector(
852  uint32_t    vector,
853  proc_ptr    new_handler,
854  proc_ptr   *old_handler
855);
856
857/*
858 *  _CPU_Install_interrupt_stack
859 *
860 *  This routine installs the hardware interrupt stack pointer.
861 *
862 *  NOTE:  It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
863 *         is TRUE.
864 */
865
866void _CPU_Install_interrupt_stack( void );
867
868/*
869 *  _CPU_Thread_Idle_body
870 *
871 *  This routine is the CPU dependent IDLE thread body.
872 *
873 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
874 *         is TRUE.
875 */
876
877void *_CPU_Thread_Idle_body( uint32_t );
878
879/*
880 *  _CPU_Context_switch
881 *
882 *  This routine switches from the run context to the heir context.
883 */
884
885void _CPU_Context_switch(
886  Context_Control  *run,
887  Context_Control  *heir
888);
889
890/*
891 *  _CPU_Context_restore
892 *
893 *  This routine is generally used only to restart self in an
894 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
895 */
896
897void _CPU_Context_restore(
898  Context_Control *new_context
899);
900
901/*
902 *  _CPU_Context_save_fp
903 *
904 *  This routine saves the floating point context passed to it.
905 */
906
907void _CPU_Context_save_fp(
908  Context_Control_fp **fp_context_ptr
909);
910
911/*
912 *  _CPU_Context_restore_fp
913 *
914 *  This routine restores the floating point context passed to it.
915 */
916
917void _CPU_Context_restore_fp(
918  Context_Control_fp **fp_context_ptr
919);
920
921
922#ifdef __cplusplus
923}
924#endif
925
926#endif
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