source: rtems/cpukit/score/cpu/sh/rtems/score/cpu.h @ 27bfcd8

5
Last change on this file since 27bfcd8 was 27bfcd8, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 25, 2017 at 1:32:02 PM

score: Delete _CPU_Context_Fp_start()

Since the FP area pointer is passed by reference in
_CPU_Context_Initialize_fp() the optional FP area adjustment via
_CPU_Context_Fp_start() is superfluous. It is also wrong with respect
to memory management, e.g. pointer passed to _Workspace_Free() may be
not the one returned by _Workspace_Allocate().

Close #1400.

  • Property mode set to 100644
File size: 20.8 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the Hitachi SH
7 *  processor.
8 *
9 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
10 *           Bernd Becker (becker@faw.uni-ulm.de)
11 *
12 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
13 *
14 *  This program is distributed in the hope that it will be useful,
15 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 *
18 *
19 *  COPYRIGHT (c) 1998-2006.
20 *  On-Line Applications Research Corporation (OAR).
21 *
22 *  The license and distribution terms for this file may be
23 *  found in the file LICENSE in this distribution or at
24 *  http://www.rtems.org/license/LICENSE.
25 */
26
27#ifndef _RTEMS_SCORE_CPU_H
28#define _RTEMS_SCORE_CPU_H
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
34#include <rtems/score/types.h>
35#include <rtems/score/sh.h>
36
37/* conditional compilation parameters */
38
39/*
40 *  Does the CPU follow the simple vectored interrupt model?
41 *
42 *  If TRUE, then RTEMS allocates the vector table it internally manages.
43 *  If FALSE, then the BSP is assumed to allocate and manage the vector
44 *  table
45 *
46 *  SH Specific Information:
47 *
48 *  XXX document implementation including references if appropriate
49 */
50#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
51
52/*
53 *  Does RTEMS manage a dedicated interrupt stack in software?
54 *
55 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
56 *  If FALSE, nothing is done.
57 *
58 *  If the CPU supports a dedicated interrupt stack in hardware,
59 *  then it is generally the responsibility of the BSP to allocate it
60 *  and set it up.
61 *
62 *  If the CPU does not support a dedicated interrupt stack, then
63 *  the porter has two options: (1) execute interrupts on the
64 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
65 *  interrupt stack.
66 *
67 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
68 *
69 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
70 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
71 *  possible that both are FALSE for a particular CPU.  Although it
72 *  is unclear what that would imply about the interrupt processing
73 *  procedure on that CPU.
74 */
75
76#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
77#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
78
79/*
80 * We define the interrupt stack in the linker script
81 */
82#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
83
84/*
85 *  Does the RTEMS invoke the user's ISR with the vector number and
86 *  a pointer to the saved interrupt frame (1) or just the vector
87 *  number (0)?
88 */
89
90#define CPU_ISR_PASSES_FRAME_POINTER FALSE
91
92/*
93 *  Does the CPU have hardware floating point?
94 *
95 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
96 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
97 *
98 *  We currently support sh1 only, which has no FPU, other SHes have an FPU
99 *
100 *  The macro name "SH_HAS_FPU" should be made CPU specific.
101 *  It indicates whether or not this CPU model has FP support.  For
102 *  example, it would be possible to have an i386_nofp CPU model
103 *  which set this to false to indicate that you have an i386 without
104 *  an i387 and wish to leave floating point support out of RTEMS.
105 */
106
107#if SH_HAS_FPU
108#define CPU_HARDWARE_FP TRUE
109#define CPU_SOFTWARE_FP FALSE
110#else
111#define CPU_SOFTWARE_FP FALSE
112#define CPU_HARDWARE_FP FALSE
113#endif
114
115/*
116 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
117 *
118 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
119 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
120 *
121 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
122 */
123
124#if SH_HAS_FPU
125#define CPU_ALL_TASKS_ARE_FP     TRUE
126#else
127#define CPU_ALL_TASKS_ARE_FP     FALSE
128#endif
129
130/*
131 *  Should the IDLE task have a floating point context?
132 *
133 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
134 *  and it has a floating point context which is switched in and out.
135 *  If FALSE, then the IDLE task does not have a floating point context.
136 *
137 *  Setting this to TRUE negatively impacts the time required to preempt
138 *  the IDLE task from an interrupt because the floating point context
139 *  must be saved as part of the preemption.
140 */
141
142#if SH_HAS_FPU
143#define CPU_IDLE_TASK_IS_FP     TRUE
144#else
145#define CPU_IDLE_TASK_IS_FP      FALSE
146#endif
147
148/*
149 *  Should the saving of the floating point registers be deferred
150 *  until a context switch is made to another different floating point
151 *  task?
152 *
153 *  If TRUE, then the floating point context will not be stored until
154 *  necessary.  It will remain in the floating point registers and not
155 *  disturned until another floating point task is switched to.
156 *
157 *  If FALSE, then the floating point context is saved when a floating
158 *  point task is switched out and restored when the next floating point
159 *  task is restored.  The state of the floating point registers between
160 *  those two operations is not specified.
161 *
162 *  If the floating point context does NOT have to be saved as part of
163 *  interrupt dispatching, then it should be safe to set this to TRUE.
164 *
165 *  Setting this flag to TRUE results in using a different algorithm
166 *  for deciding when to save and restore the floating point context.
167 *  The deferred FP switch algorithm minimizes the number of times
168 *  the FP context is saved and restored.  The FP context is not saved
169 *  until a context switch is made to another, different FP task.
170 *  Thus in a system with only one FP task, the FP context will never
171 *  be saved or restored.
172 */
173
174#if SH_HAS_FPU
175#define CPU_USE_DEFERRED_FP_SWITCH      FALSE
176#else
177#define CPU_USE_DEFERRED_FP_SWITCH      TRUE
178#endif
179
180#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
181
182/*
183 *  Does this port provide a CPU dependent IDLE task implementation?
184 *
185 *  If TRUE, then the routine _CPU_Thread_Idle_body
186 *  must be provided and is the default IDLE thread body instead of
187 *  _CPU_Thread_Idle_body.
188 *
189 *  If FALSE, then use the generic IDLE thread body if the BSP does
190 *  not provide one.
191 *
192 *  This is intended to allow for supporting processors which have
193 *  a low power or idle mode.  When the IDLE thread is executed, then
194 *  the CPU can be powered down.
195 *
196 *  The order of precedence for selecting the IDLE thread body is:
197 *
198 *    1.  BSP provided
199 *    2.  CPU dependent (if provided)
200 *    3.  generic (if no BSP and no CPU dependent)
201 */
202
203#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
204
205/*
206 *  Does the stack grow up (toward higher addresses) or down
207 *  (toward lower addresses)?
208 *
209 *  If TRUE, then the grows upward.
210 *  If FALSE, then the grows toward smaller addresses.
211 */
212
213#define CPU_STACK_GROWS_UP               FALSE
214
215/* FIXME: Is this the right value? */
216#define CPU_CACHE_LINE_BYTES 16
217
218#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
219
220/*
221 *  The following defines the number of bits actually used in the
222 *  interrupt field of the task mode.  How those bits map to the
223 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
224 */
225
226#define CPU_MODES_INTERRUPT_MASK   0x0000000f
227
228#define CPU_MAXIMUM_PROCESSORS 32
229
230/*
231 *  Processor defined structures required for cpukit/score.
232 */
233
234/* may need to put some structures here.  */
235
236/*
237 * Contexts
238 *
239 *  Generally there are 2 types of context to save.
240 *     1. Interrupt registers to save
241 *     2. Task level registers to save
242 *
243 *  This means we have the following 3 context items:
244 *     1. task level context stuff::  Context_Control
245 *     2. floating point task stuff:: Context_Control_fp
246 *     3. special interrupt level context :: Context_Control_interrupt
247 *
248 *  On some processors, it is cost-effective to save only the callee
249 *  preserved registers during a task context switch.  This means
250 *  that the ISR code needs to save those registers which do not
251 *  persist across function calls.  It is not mandatory to make this
252 *  distinctions between the caller/callee saves registers for the
253 *  purpose of minimizing context saved during task switch and on interrupts.
254 *  If the cost of saving extra registers is minimal, simplicity is the
255 *  choice.  Save the same context on interrupt entry as for tasks in
256 *  this case.
257 *
258 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
259 *  care should be used in designing the context area.
260 *
261 *  On some CPUs with hardware floating point support, the Context_Control_fp
262 *  structure will not be used or it simply consist of an array of a
263 *  fixed number of bytes.   This is done when the floating point context
264 *  is dumped by a "FP save context" type instruction and the format
265 *  is not really defined by the CPU.  In this case, there is no need
266 *  to figure out the exact format -- only the size.  Of course, although
267 *  this is enough information for RTEMS, it is probably not enough for
268 *  a debugger such as gdb.  But that is another problem.
269 */
270
271typedef struct {
272  uint32_t   *r15;      /* stack pointer */
273
274  uint32_t   macl;
275  uint32_t   mach;
276  uint32_t   *pr;
277
278  uint32_t   *r14;      /* frame pointer/call saved */
279
280  uint32_t   r13;       /* call saved */
281  uint32_t   r12;       /* call saved */
282  uint32_t   r11;       /* call saved */
283  uint32_t   r10;       /* call saved */
284  uint32_t   r9;        /* call saved */
285  uint32_t   r8;        /* call saved */
286
287  uint32_t   *r7;       /* arg in */
288  uint32_t   *r6;       /* arg in */
289
290#if 0
291  uint32_t   *r5;       /* arg in */
292  uint32_t   *r4;       /* arg in */
293#endif
294
295  uint32_t   *r3;       /* scratch */
296  uint32_t   *r2;       /* scratch */
297  uint32_t   *r1;       /* scratch */
298
299  uint32_t   *r0;       /* arg return */
300
301  uint32_t   gbr;
302  uint32_t   sr;
303
304} Context_Control;
305
306#define _CPU_Context_Get_SP( _context ) \
307  (_context)->r15
308
309typedef struct {
310#if SH_HAS_FPU
311#ifdef SH4_USE_X_REGISTERS
312  union {
313    float f[16];
314    double d[8];
315  } x;
316#endif
317  union {
318    float f[16];
319    double d[8];
320  } r;
321  float fpul;       /* fp communication register */
322  uint32_t   fpscr; /* fp control register */
323#endif /* SH_HAS_FPU */
324} Context_Control_fp;
325
326typedef struct {
327} CPU_Interrupt_frame;
328
329/*
330 *  This variable is optional.  It is used on CPUs on which it is difficult
331 *  to generate an "uninitialized" FP context.  It is filled in by
332 *  _CPU_Initialize and copied into the task's FP context area during
333 *  _CPU_Context_Initialize.
334 */
335
336#if SH_HAS_FPU
337extern Context_Control_fp _CPU_Null_fp_context;
338#endif
339
340/*
341 *  Nothing prevents the porter from declaring more CPU specific variables.
342 */
343
344/* XXX: if needed, put more variables here */
345void CPU_delay( uint32_t   microseconds );
346
347/*
348 *  The size of the floating point context area.  On some CPUs this
349 *  will not be a "sizeof" because the format of the floating point
350 *  area is not defined -- only the size is.  This is usually on
351 *  CPUs with a "floating point save context" instruction.
352 */
353
354#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
355
356/*
357 *  Amount of extra stack (above minimum stack size) required by
358 *  MPCI receive server thread.  Remember that in a multiprocessor
359 *  system this thread must exist and be able to process all directives.
360 */
361
362#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
363
364/*
365 *  This defines the number of entries in the ISR_Vector_table managed
366 *  by RTEMS.
367 */
368
369#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
370#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
371
372/*
373 *  This is defined if the port has a special way to report the ISR nesting
374 *  level.  Most ports maintain the variable _ISR_Nest_level.
375 */
376
377#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
378
379/*
380 *  Should be large enough to run all RTEMS tests.  This ensures
381 *  that a "reasonable" small application should not have any problems.
382 *
383 *  We have been able to run the sptests with this value, but have not
384 *  been able to run the tmtest suite.
385 */
386
387#define CPU_STACK_MINIMUM_SIZE          4096
388
389#define CPU_SIZEOF_POINTER 4
390
391/*
392 *  CPU's worst alignment requirement for data types on a byte boundary.  This
393 *  alignment does not take into account the requirements for the stack.
394 */
395#if defined(__SH4__)
396/* FIXME: sh3 and SH3E? */
397#define CPU_ALIGNMENT              8
398#else
399#define CPU_ALIGNMENT              4
400#endif
401
402/*
403 *  This number corresponds to the byte alignment requirement for the
404 *  heap handler.  This alignment requirement may be stricter than that
405 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
406 *  common for the heap to follow the same alignment requirement as
407 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
408 *  then this should be set to CPU_ALIGNMENT.
409 *
410 *  NOTE:  This does not have to be a power of 2.  It does have to
411 *         be greater or equal to than CPU_ALIGNMENT.
412 */
413
414#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
415
416/*
417 *  This number corresponds to the byte alignment requirement for memory
418 *  buffers allocated by the partition manager.  This alignment requirement
419 *  may be stricter than that for the data types alignment specified by
420 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
421 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
422 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
423 *
424 *  NOTE:  This does not have to be a power of 2.  It does have to
425 *         be greater or equal to than CPU_ALIGNMENT.
426 */
427
428#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
429
430/*
431 *  This number corresponds to the byte alignment requirement for the
432 *  stack.  This alignment requirement may be stricter than that for the
433 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
434 *  is strict enough for the stack, then this should be set to 0.
435 *
436 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
437 */
438
439#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
440
441/*
442 *  ISR handler macros
443 */
444
445/*
446 *  Support routine to initialize the RTEMS vector table after it is allocated.
447 *
448 *  SH Specific Information: NONE
449 */
450
451#define _CPU_Initialize_vectors()
452
453/*
454 *  Disable all interrupts for an RTEMS critical section.  The previous
455 *  level is returned in _level.
456 */
457
458#define _CPU_ISR_Disable( _level) \
459  sh_disable_interrupts( _level )
460
461/*
462 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
463 *  This indicates the end of an RTEMS critical section.  The parameter
464 *  _level is not modified.
465 */
466
467#define _CPU_ISR_Enable( _level) \
468   sh_enable_interrupts( _level)
469
470/*
471 *  This temporarily restores the interrupt to _level before immediately
472 *  disabling them again.  This is used to divide long RTEMS critical
473 *  sections into two or more parts.  The parameter _level is not
474 * modified.
475 */
476
477#define _CPU_ISR_Flash( _level) \
478  sh_flash_interrupts( _level)
479
480RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
481{
482  sh_get_interrupt_level( level );
483  return level == 0;
484}
485
486/*
487 *  Map interrupt level in task mode onto the hardware that the CPU
488 *  actually provides.  Currently, interrupt levels which do not
489 *  map onto the CPU in a generic fashion are undefined.  Someday,
490 *  it would be nice if these were "mapped" by the application
491 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
492 *  8 - 255 would be available for bsp/application specific meaning.
493 *  This could be used to manage a programmable interrupt controller
494 *  via the rtems_task_mode directive.
495 */
496
497#define _CPU_ISR_Set_level( _newlevel) \
498  sh_set_interrupt_level(_newlevel)
499
500uint32_t   _CPU_ISR_Get_level( void );
501
502/* end of ISR handler macros */
503
504/* Context handler macros */
505
506/*
507 *  Initialize the context to a state suitable for starting a
508 *  task after a context restore operation.  Generally, this
509 *  involves:
510 *
511 *     - setting a starting address
512 *     - preparing the stack
513 *     - preparing the stack and frame pointers
514 *     - setting the proper interrupt level in the context
515 *     - initializing the floating point context
516 *
517 *  This routine generally does not set any unnecessary register
518 *  in the context.  The state of the "general data" registers is
519 *  undefined at task start time.
520 *
521 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
522 *        point thread.  This is typically only used on CPUs where the
523 *        FPU may be easily disabled by software such as on the SPARC
524 *        where the PSR contains an enable FPU bit.
525 */
526
527/*
528 * FIXME: defined as a function for debugging - should be a macro
529 */
530void _CPU_Context_Initialize(
531  Context_Control       *_the_context,
532  void                  *_stack_base,
533  uint32_t              _size,
534  uint32_t              _isr,
535  void    (*_entry_point)(void),
536  int                   _is_fp,
537  void                  *_tls_area );
538
539/*
540 *  This routine is responsible for somehow restarting the currently
541 *  executing task.  If you are lucky, then all that is necessary
542 *  is restoring the context.  Otherwise, there will need to be
543 *  a special assembly routine which does something special in this
544 *  case.  Context_Restore should work most of the time.  It will
545 *  not work if restarting self conflicts with the stack frame
546 *  assumptions of restoring a context.
547 */
548
549#define _CPU_Context_Restart_self( _the_context ) \
550   _CPU_Context_restore( (_the_context) );
551
552/*
553 *  This routine initializes the FP context area passed to it to.
554 *  There are a few standard ways in which to initialize the
555 *  floating point context.  The code included for this macro assumes
556 *  that this is a CPU in which a "initial" FP context was saved into
557 *  _CPU_Null_fp_context and it simply copies it to the destination
558 *  context passed to it.
559 *
560 *  Other models include (1) not doing anything, and (2) putting
561 *  a "null FP status word" in the correct place in the FP context.
562 *  SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have.
563 */
564
565#if SH_HAS_FPU
566#define _CPU_Context_Initialize_fp( _destination ) \
567  do { \
568     *(*(_destination)) = _CPU_Null_fp_context;\
569  } while(0)
570#else
571#define _CPU_Context_Initialize_fp( _destination ) \
572  {  }
573#endif
574
575/* end of Context handler macros */
576
577/* Fatal Error manager macros */
578
579/*
580 * FIXME: Trap32 ???
581 *
582 *  This routine copies _error into a known place -- typically a stack
583 *  location or a register, optionally disables interrupts, and
584 *  invokes a Trap32 Instruction which returns to the breakpoint
585 *  routine of cmon.
586 */
587
588#ifdef BSP_FATAL_HALT
589  /* we manage the fatal error in the board support package */
590  void bsp_fatal_halt( uint32_t   _error);
591#define _CPU_Fatal_halt( _source, _error ) bsp_fatal_halt( _error)
592#else
593#define _CPU_Fatal_halt( _source, _error)\
594{ \
595  __asm__ volatile("mov.l %0,r0"::"m" (_error)); \
596  __asm__ volatile("mov #1, r4"); \
597  __asm__ volatile("trapa #34"); \
598}
599#endif
600
601/* end of Fatal Error manager macros */
602
603#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
604
605/* functions */
606
607/*
608 *  @brief CPU Initialize
609 *
610 *  _CPU_Initialize
611 *
612 *  This routine performs CPU dependent initialization.
613 */
614void _CPU_Initialize(void);
615
616/*
617 *  _CPU_ISR_install_raw_handler
618 *
619 *  This routine installs a "raw" interrupt handler directly into the
620 *  processor's vector table.
621 */
622
623void _CPU_ISR_install_raw_handler(
624  uint32_t    vector,
625  proc_ptr    new_handler,
626  proc_ptr   *old_handler
627);
628
629/*
630 *  _CPU_ISR_install_vector
631 *
632 *  This routine installs an interrupt vector.
633 */
634
635void _CPU_ISR_install_vector(
636  uint32_t    vector,
637  proc_ptr    new_handler,
638  proc_ptr   *old_handler
639);
640
641/*
642 *  _CPU_Install_interrupt_stack
643 *
644 *  This routine installs the hardware interrupt stack pointer.
645 *
646 *  NOTE:  It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
647 *         is TRUE.
648 */
649
650void _CPU_Install_interrupt_stack( void );
651
652/*
653 *  _CPU_Thread_Idle_body
654 *
655 *  This routine is the CPU dependent IDLE thread body.
656 *
657 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
658 *         is TRUE.
659 */
660
661void *_CPU_Thread_Idle_body( uintptr_t ignored );
662
663/*
664 *  _CPU_Context_switch
665 *
666 *  This routine switches from the run context to the heir context.
667 */
668
669void _CPU_Context_switch(
670  Context_Control  *run,
671  Context_Control  *heir
672);
673
674/*
675 *  _CPU_Context_restore
676 *
677 *  This routine is generally used only to restart self in an
678 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
679 */
680
681void _CPU_Context_restore(
682  Context_Control *new_context
683) RTEMS_NO_RETURN;
684
685/*
686 *  @brief This routine saves the floating point context passed to it.
687 *
688 *  _CPU_Context_save_fp
689 *
690 */
691void _CPU_Context_save_fp(
692  Context_Control_fp **fp_context_ptr
693);
694
695/*
696 *  @brief This routine restores the floating point context passed to it.
697 *
698 *  _CPU_Context_restore_fp
699 *
700 */
701void _CPU_Context_restore_fp(
702  Context_Control_fp **fp_context_ptr
703);
704
705static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
706{
707  /* TODO */
708}
709
710static inline void _CPU_Context_validate( uintptr_t pattern )
711{
712  while (1) {
713    /* TODO */
714  }
715}
716
717/* FIXME */
718typedef CPU_Interrupt_frame CPU_Exception_frame;
719
720void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
721
722typedef uint32_t CPU_Counter_ticks;
723
724CPU_Counter_ticks _CPU_Counter_read( void );
725
726static inline CPU_Counter_ticks _CPU_Counter_difference(
727  CPU_Counter_ticks second,
728  CPU_Counter_ticks first
729)
730{
731  return second - first;
732}
733
734#ifdef __cplusplus
735}
736#endif
737
738#endif
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