1 | /** |
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2 | * @file rtems/score/cpu.h |
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3 | */ |
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4 | |
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5 | /* |
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6 | * This include file contains information pertaining to the Hitachi SH |
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7 | * processor. |
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8 | * |
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9 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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10 | * Bernd Becker (becker@faw.uni-ulm.de) |
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11 | * |
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12 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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13 | * |
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14 | * This program is distributed in the hope that it will be useful, |
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15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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17 | * |
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18 | * |
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19 | * COPYRIGHT (c) 1998-2006. |
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20 | * On-Line Applications Research Corporation (OAR). |
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21 | * |
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22 | * The license and distribution terms for this file may be |
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23 | * found in the file LICENSE in this distribution or at |
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24 | * http://www.rtems.org/license/LICENSE. |
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25 | */ |
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26 | |
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27 | #ifndef _RTEMS_SCORE_CPU_H |
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28 | #define _RTEMS_SCORE_CPU_H |
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29 | |
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30 | #ifdef __cplusplus |
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31 | extern "C" { |
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32 | #endif |
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33 | |
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34 | #include <rtems/score/types.h> |
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35 | #include <rtems/score/sh.h> |
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36 | |
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37 | /* conditional compilation parameters */ |
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38 | |
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39 | /* |
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40 | * Does the CPU follow the simple vectored interrupt model? |
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41 | * |
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42 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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43 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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44 | * table |
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45 | * |
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46 | * SH Specific Information: |
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47 | * |
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48 | * XXX document implementation including references if appropriate |
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49 | */ |
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50 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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51 | |
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52 | /* |
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53 | * Does RTEMS manage a dedicated interrupt stack in software? |
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54 | * |
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55 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
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56 | * If FALSE, nothing is done. |
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57 | * |
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58 | * If the CPU supports a dedicated interrupt stack in hardware, |
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59 | * then it is generally the responsibility of the BSP to allocate it |
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60 | * and set it up. |
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61 | * |
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62 | * If the CPU does not support a dedicated interrupt stack, then |
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63 | * the porter has two options: (1) execute interrupts on the |
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64 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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65 | * interrupt stack. |
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66 | * |
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67 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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68 | * |
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69 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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70 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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71 | * possible that both are FALSE for a particular CPU. Although it |
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72 | * is unclear what that would imply about the interrupt processing |
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73 | * procedure on that CPU. |
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74 | */ |
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75 | |
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76 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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77 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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78 | |
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79 | /* |
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80 | * We define the interrupt stack in the linker script |
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81 | */ |
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82 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
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83 | |
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84 | /* |
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85 | * Does the RTEMS invoke the user's ISR with the vector number and |
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86 | * a pointer to the saved interrupt frame (1) or just the vector |
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87 | * number (0)? |
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88 | */ |
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89 | |
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90 | #define CPU_ISR_PASSES_FRAME_POINTER FALSE |
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91 | |
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92 | /* |
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93 | * Does the CPU have hardware floating point? |
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94 | * |
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95 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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96 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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97 | * |
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98 | * We currently support sh1 only, which has no FPU, other SHes have an FPU |
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99 | * |
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100 | * The macro name "SH_HAS_FPU" should be made CPU specific. |
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101 | * It indicates whether or not this CPU model has FP support. For |
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102 | * example, it would be possible to have an i386_nofp CPU model |
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103 | * which set this to false to indicate that you have an i386 without |
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104 | * an i387 and wish to leave floating point support out of RTEMS. |
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105 | */ |
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106 | |
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107 | #if SH_HAS_FPU |
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108 | #define CPU_HARDWARE_FP TRUE |
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109 | #define CPU_SOFTWARE_FP FALSE |
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110 | #else |
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111 | #define CPU_SOFTWARE_FP FALSE |
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112 | #define CPU_HARDWARE_FP FALSE |
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113 | #endif |
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114 | |
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115 | /* |
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116 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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117 | * |
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118 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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119 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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120 | * |
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121 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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122 | */ |
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123 | |
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124 | #if SH_HAS_FPU |
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125 | #define CPU_ALL_TASKS_ARE_FP TRUE |
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126 | #else |
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127 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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128 | #endif |
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129 | |
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130 | /* |
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131 | * Should the IDLE task have a floating point context? |
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132 | * |
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133 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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134 | * and it has a floating point context which is switched in and out. |
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135 | * If FALSE, then the IDLE task does not have a floating point context. |
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136 | * |
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137 | * Setting this to TRUE negatively impacts the time required to preempt |
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138 | * the IDLE task from an interrupt because the floating point context |
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139 | * must be saved as part of the preemption. |
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140 | */ |
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141 | |
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142 | #if SH_HAS_FPU |
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143 | #define CPU_IDLE_TASK_IS_FP TRUE |
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144 | #else |
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145 | #define CPU_IDLE_TASK_IS_FP FALSE |
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146 | #endif |
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147 | |
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148 | /* |
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149 | * Should the saving of the floating point registers be deferred |
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150 | * until a context switch is made to another different floating point |
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151 | * task? |
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152 | * |
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153 | * If TRUE, then the floating point context will not be stored until |
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154 | * necessary. It will remain in the floating point registers and not |
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155 | * disturned until another floating point task is switched to. |
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156 | * |
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157 | * If FALSE, then the floating point context is saved when a floating |
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158 | * point task is switched out and restored when the next floating point |
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159 | * task is restored. The state of the floating point registers between |
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160 | * those two operations is not specified. |
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161 | * |
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162 | * If the floating point context does NOT have to be saved as part of |
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163 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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164 | * |
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165 | * Setting this flag to TRUE results in using a different algorithm |
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166 | * for deciding when to save and restore the floating point context. |
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167 | * The deferred FP switch algorithm minimizes the number of times |
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168 | * the FP context is saved and restored. The FP context is not saved |
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169 | * until a context switch is made to another, different FP task. |
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170 | * Thus in a system with only one FP task, the FP context will never |
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171 | * be saved or restored. |
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172 | */ |
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173 | |
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174 | #if SH_HAS_FPU |
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175 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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176 | #else |
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177 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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178 | #endif |
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179 | |
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180 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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181 | |
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182 | /* |
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183 | * Does this port provide a CPU dependent IDLE task implementation? |
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184 | * |
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185 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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186 | * must be provided and is the default IDLE thread body instead of |
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187 | * _CPU_Thread_Idle_body. |
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188 | * |
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189 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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190 | * not provide one. |
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191 | * |
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192 | * This is intended to allow for supporting processors which have |
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193 | * a low power or idle mode. When the IDLE thread is executed, then |
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194 | * the CPU can be powered down. |
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195 | * |
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196 | * The order of precedence for selecting the IDLE thread body is: |
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197 | * |
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198 | * 1. BSP provided |
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199 | * 2. CPU dependent (if provided) |
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200 | * 3. generic (if no BSP and no CPU dependent) |
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201 | */ |
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202 | |
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203 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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204 | |
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205 | /* |
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206 | * Does the stack grow up (toward higher addresses) or down |
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207 | * (toward lower addresses)? |
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208 | * |
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209 | * If TRUE, then the grows upward. |
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210 | * If FALSE, then the grows toward smaller addresses. |
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211 | */ |
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212 | |
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213 | #define CPU_STACK_GROWS_UP FALSE |
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214 | |
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215 | /* FIXME: Is this the right value? */ |
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216 | #define CPU_CACHE_LINE_BYTES 16 |
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217 | |
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218 | #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
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219 | |
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220 | /* |
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221 | * The following defines the number of bits actually used in the |
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222 | * interrupt field of the task mode. How those bits map to the |
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223 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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224 | */ |
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225 | |
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226 | #define CPU_MODES_INTERRUPT_MASK 0x0000000f |
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227 | |
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228 | #define CPU_MAXIMUM_PROCESSORS 32 |
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229 | |
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230 | /* |
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231 | * Processor defined structures required for cpukit/score. |
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232 | */ |
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233 | |
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234 | /* may need to put some structures here. */ |
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235 | |
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236 | /* |
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237 | * Contexts |
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238 | * |
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239 | * Generally there are 2 types of context to save. |
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240 | * 1. Interrupt registers to save |
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241 | * 2. Task level registers to save |
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242 | * |
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243 | * This means we have the following 3 context items: |
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244 | * 1. task level context stuff:: Context_Control |
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245 | * 2. floating point task stuff:: Context_Control_fp |
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246 | * 3. special interrupt level context :: Context_Control_interrupt |
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247 | * |
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248 | * On some processors, it is cost-effective to save only the callee |
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249 | * preserved registers during a task context switch. This means |
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250 | * that the ISR code needs to save those registers which do not |
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251 | * persist across function calls. It is not mandatory to make this |
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252 | * distinctions between the caller/callee saves registers for the |
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253 | * purpose of minimizing context saved during task switch and on interrupts. |
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254 | * If the cost of saving extra registers is minimal, simplicity is the |
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255 | * choice. Save the same context on interrupt entry as for tasks in |
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256 | * this case. |
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257 | * |
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258 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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259 | * care should be used in designing the context area. |
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260 | * |
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261 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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262 | * structure will not be used or it simply consist of an array of a |
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263 | * fixed number of bytes. This is done when the floating point context |
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264 | * is dumped by a "FP save context" type instruction and the format |
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265 | * is not really defined by the CPU. In this case, there is no need |
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266 | * to figure out the exact format -- only the size. Of course, although |
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267 | * this is enough information for RTEMS, it is probably not enough for |
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268 | * a debugger such as gdb. But that is another problem. |
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269 | */ |
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270 | |
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271 | typedef struct { |
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272 | uint32_t *r15; /* stack pointer */ |
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273 | |
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274 | uint32_t macl; |
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275 | uint32_t mach; |
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276 | uint32_t *pr; |
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277 | |
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278 | uint32_t *r14; /* frame pointer/call saved */ |
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279 | |
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280 | uint32_t r13; /* call saved */ |
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281 | uint32_t r12; /* call saved */ |
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282 | uint32_t r11; /* call saved */ |
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283 | uint32_t r10; /* call saved */ |
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284 | uint32_t r9; /* call saved */ |
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285 | uint32_t r8; /* call saved */ |
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286 | |
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287 | uint32_t *r7; /* arg in */ |
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288 | uint32_t *r6; /* arg in */ |
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289 | |
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290 | #if 0 |
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291 | uint32_t *r5; /* arg in */ |
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292 | uint32_t *r4; /* arg in */ |
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293 | #endif |
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294 | |
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295 | uint32_t *r3; /* scratch */ |
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296 | uint32_t *r2; /* scratch */ |
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297 | uint32_t *r1; /* scratch */ |
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298 | |
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299 | uint32_t *r0; /* arg return */ |
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300 | |
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301 | uint32_t gbr; |
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302 | uint32_t sr; |
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303 | |
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304 | } Context_Control; |
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305 | |
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306 | #define _CPU_Context_Get_SP( _context ) \ |
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307 | (_context)->r15 |
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308 | |
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309 | typedef struct { |
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310 | #if SH_HAS_FPU |
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311 | #ifdef SH4_USE_X_REGISTERS |
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312 | union { |
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313 | float f[16]; |
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314 | double d[8]; |
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315 | } x; |
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316 | #endif |
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317 | union { |
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318 | float f[16]; |
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319 | double d[8]; |
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320 | } r; |
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321 | float fpul; /* fp communication register */ |
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322 | uint32_t fpscr; /* fp control register */ |
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323 | #endif /* SH_HAS_FPU */ |
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324 | } Context_Control_fp; |
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325 | |
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326 | typedef struct { |
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327 | } CPU_Interrupt_frame; |
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328 | |
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329 | /* |
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330 | * This variable is optional. It is used on CPUs on which it is difficult |
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331 | * to generate an "uninitialized" FP context. It is filled in by |
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332 | * _CPU_Initialize and copied into the task's FP context area during |
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333 | * _CPU_Context_Initialize. |
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334 | */ |
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335 | |
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336 | #if SH_HAS_FPU |
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337 | extern Context_Control_fp _CPU_Null_fp_context; |
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338 | #endif |
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339 | |
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340 | /* |
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341 | * Nothing prevents the porter from declaring more CPU specific variables. |
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342 | */ |
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343 | |
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344 | /* XXX: if needed, put more variables here */ |
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345 | void CPU_delay( uint32_t microseconds ); |
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346 | |
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347 | /* |
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348 | * The size of the floating point context area. On some CPUs this |
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349 | * will not be a "sizeof" because the format of the floating point |
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350 | * area is not defined -- only the size is. This is usually on |
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351 | * CPUs with a "floating point save context" instruction. |
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352 | */ |
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353 | |
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354 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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355 | |
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356 | /* |
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357 | * Amount of extra stack (above minimum stack size) required by |
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358 | * MPCI receive server thread. Remember that in a multiprocessor |
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359 | * system this thread must exist and be able to process all directives. |
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360 | */ |
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361 | |
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362 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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363 | |
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364 | /* |
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365 | * This defines the number of entries in the ISR_Vector_table managed |
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366 | * by RTEMS. |
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367 | */ |
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368 | |
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369 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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370 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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371 | |
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372 | /* |
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373 | * This is defined if the port has a special way to report the ISR nesting |
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374 | * level. Most ports maintain the variable _ISR_Nest_level. |
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375 | */ |
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376 | |
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377 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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378 | |
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379 | /* |
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380 | * Should be large enough to run all RTEMS tests. This ensures |
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381 | * that a "reasonable" small application should not have any problems. |
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382 | * |
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383 | * We have been able to run the sptests with this value, but have not |
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384 | * been able to run the tmtest suite. |
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385 | */ |
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386 | |
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387 | #define CPU_STACK_MINIMUM_SIZE 4096 |
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388 | |
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389 | #define CPU_SIZEOF_POINTER 4 |
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390 | |
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391 | /* |
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392 | * CPU's worst alignment requirement for data types on a byte boundary. This |
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393 | * alignment does not take into account the requirements for the stack. |
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394 | */ |
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395 | #if defined(__SH4__) |
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396 | /* FIXME: sh3 and SH3E? */ |
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397 | #define CPU_ALIGNMENT 8 |
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398 | #else |
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399 | #define CPU_ALIGNMENT 4 |
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400 | #endif |
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401 | |
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402 | /* |
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403 | * This number corresponds to the byte alignment requirement for the |
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404 | * heap handler. This alignment requirement may be stricter than that |
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405 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
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406 | * common for the heap to follow the same alignment requirement as |
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407 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
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408 | * then this should be set to CPU_ALIGNMENT. |
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409 | * |
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410 | * NOTE: This does not have to be a power of 2. It does have to |
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411 | * be greater or equal to than CPU_ALIGNMENT. |
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412 | */ |
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413 | |
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414 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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415 | |
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416 | /* |
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417 | * This number corresponds to the byte alignment requirement for memory |
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418 | * buffers allocated by the partition manager. This alignment requirement |
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419 | * may be stricter than that for the data types alignment specified by |
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420 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
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421 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
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422 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
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423 | * |
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424 | * NOTE: This does not have to be a power of 2. It does have to |
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425 | * be greater or equal to than CPU_ALIGNMENT. |
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426 | */ |
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427 | |
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428 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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429 | |
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430 | /* |
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431 | * This number corresponds to the byte alignment requirement for the |
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432 | * stack. This alignment requirement may be stricter than that for the |
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433 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
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434 | * is strict enough for the stack, then this should be set to 0. |
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435 | * |
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436 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
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437 | */ |
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438 | |
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439 | #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT |
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440 | |
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441 | /* |
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442 | * ISR handler macros |
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443 | */ |
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444 | |
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445 | /* |
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446 | * Support routine to initialize the RTEMS vector table after it is allocated. |
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447 | * |
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448 | * SH Specific Information: NONE |
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449 | */ |
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450 | |
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451 | #define _CPU_Initialize_vectors() |
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452 | |
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453 | /* |
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454 | * Disable all interrupts for an RTEMS critical section. The previous |
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455 | * level is returned in _level. |
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456 | */ |
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457 | |
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458 | #define _CPU_ISR_Disable( _level) \ |
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459 | sh_disable_interrupts( _level ) |
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460 | |
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461 | /* |
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462 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
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463 | * This indicates the end of an RTEMS critical section. The parameter |
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464 | * _level is not modified. |
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465 | */ |
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466 | |
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467 | #define _CPU_ISR_Enable( _level) \ |
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468 | sh_enable_interrupts( _level) |
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469 | |
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470 | /* |
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471 | * This temporarily restores the interrupt to _level before immediately |
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472 | * disabling them again. This is used to divide long RTEMS critical |
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473 | * sections into two or more parts. The parameter _level is not |
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474 | * modified. |
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475 | */ |
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476 | |
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477 | #define _CPU_ISR_Flash( _level) \ |
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478 | sh_flash_interrupts( _level) |
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479 | |
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480 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
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481 | { |
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482 | sh_get_interrupt_level( level ); |
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483 | return level == 0; |
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484 | } |
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485 | |
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486 | /* |
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487 | * Map interrupt level in task mode onto the hardware that the CPU |
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488 | * actually provides. Currently, interrupt levels which do not |
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489 | * map onto the CPU in a generic fashion are undefined. Someday, |
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490 | * it would be nice if these were "mapped" by the application |
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491 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
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492 | * 8 - 255 would be available for bsp/application specific meaning. |
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493 | * This could be used to manage a programmable interrupt controller |
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494 | * via the rtems_task_mode directive. |
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495 | */ |
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496 | |
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497 | #define _CPU_ISR_Set_level( _newlevel) \ |
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498 | sh_set_interrupt_level(_newlevel) |
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499 | |
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500 | uint32_t _CPU_ISR_Get_level( void ); |
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501 | |
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502 | /* end of ISR handler macros */ |
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503 | |
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504 | /* Context handler macros */ |
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505 | |
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506 | /* |
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507 | * Initialize the context to a state suitable for starting a |
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508 | * task after a context restore operation. Generally, this |
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509 | * involves: |
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510 | * |
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511 | * - setting a starting address |
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512 | * - preparing the stack |
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513 | * - preparing the stack and frame pointers |
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514 | * - setting the proper interrupt level in the context |
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515 | * - initializing the floating point context |
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516 | * |
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517 | * This routine generally does not set any unnecessary register |
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518 | * in the context. The state of the "general data" registers is |
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519 | * undefined at task start time. |
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520 | * |
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521 | * NOTE: This is_fp parameter is TRUE if the thread is to be a floating |
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522 | * point thread. This is typically only used on CPUs where the |
---|
523 | * FPU may be easily disabled by software such as on the SPARC |
---|
524 | * where the PSR contains an enable FPU bit. |
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525 | */ |
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526 | |
---|
527 | /* |
---|
528 | * FIXME: defined as a function for debugging - should be a macro |
---|
529 | */ |
---|
530 | void _CPU_Context_Initialize( |
---|
531 | Context_Control *_the_context, |
---|
532 | void *_stack_base, |
---|
533 | uint32_t _size, |
---|
534 | uint32_t _isr, |
---|
535 | void (*_entry_point)(void), |
---|
536 | int _is_fp, |
---|
537 | void *_tls_area ); |
---|
538 | |
---|
539 | /* |
---|
540 | * This routine is responsible for somehow restarting the currently |
---|
541 | * executing task. If you are lucky, then all that is necessary |
---|
542 | * is restoring the context. Otherwise, there will need to be |
---|
543 | * a special assembly routine which does something special in this |
---|
544 | * case. Context_Restore should work most of the time. It will |
---|
545 | * not work if restarting self conflicts with the stack frame |
---|
546 | * assumptions of restoring a context. |
---|
547 | */ |
---|
548 | |
---|
549 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
550 | _CPU_Context_restore( (_the_context) ); |
---|
551 | |
---|
552 | /* |
---|
553 | * This routine initializes the FP context area passed to it to. |
---|
554 | * There are a few standard ways in which to initialize the |
---|
555 | * floating point context. The code included for this macro assumes |
---|
556 | * that this is a CPU in which a "initial" FP context was saved into |
---|
557 | * _CPU_Null_fp_context and it simply copies it to the destination |
---|
558 | * context passed to it. |
---|
559 | * |
---|
560 | * Other models include (1) not doing anything, and (2) putting |
---|
561 | * a "null FP status word" in the correct place in the FP context. |
---|
562 | * SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have. |
---|
563 | */ |
---|
564 | |
---|
565 | #if SH_HAS_FPU |
---|
566 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
567 | do { \ |
---|
568 | *(*(_destination)) = _CPU_Null_fp_context;\ |
---|
569 | } while(0) |
---|
570 | #else |
---|
571 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
572 | { } |
---|
573 | #endif |
---|
574 | |
---|
575 | /* end of Context handler macros */ |
---|
576 | |
---|
577 | /* Fatal Error manager macros */ |
---|
578 | |
---|
579 | /* |
---|
580 | * FIXME: Trap32 ??? |
---|
581 | * |
---|
582 | * This routine copies _error into a known place -- typically a stack |
---|
583 | * location or a register, optionally disables interrupts, and |
---|
584 | * invokes a Trap32 Instruction which returns to the breakpoint |
---|
585 | * routine of cmon. |
---|
586 | */ |
---|
587 | |
---|
588 | #ifdef BSP_FATAL_HALT |
---|
589 | /* we manage the fatal error in the board support package */ |
---|
590 | void bsp_fatal_halt( uint32_t _error); |
---|
591 | #define _CPU_Fatal_halt( _source, _error ) bsp_fatal_halt( _error) |
---|
592 | #else |
---|
593 | #define _CPU_Fatal_halt( _source, _error)\ |
---|
594 | { \ |
---|
595 | __asm__ volatile("mov.l %0,r0"::"m" (_error)); \ |
---|
596 | __asm__ volatile("mov #1, r4"); \ |
---|
597 | __asm__ volatile("trapa #34"); \ |
---|
598 | } |
---|
599 | #endif |
---|
600 | |
---|
601 | /* end of Fatal Error manager macros */ |
---|
602 | |
---|
603 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
604 | |
---|
605 | /* functions */ |
---|
606 | |
---|
607 | /* |
---|
608 | * @brief CPU Initialize |
---|
609 | * |
---|
610 | * _CPU_Initialize |
---|
611 | * |
---|
612 | * This routine performs CPU dependent initialization. |
---|
613 | */ |
---|
614 | void _CPU_Initialize(void); |
---|
615 | |
---|
616 | /* |
---|
617 | * _CPU_ISR_install_raw_handler |
---|
618 | * |
---|
619 | * This routine installs a "raw" interrupt handler directly into the |
---|
620 | * processor's vector table. |
---|
621 | */ |
---|
622 | |
---|
623 | void _CPU_ISR_install_raw_handler( |
---|
624 | uint32_t vector, |
---|
625 | proc_ptr new_handler, |
---|
626 | proc_ptr *old_handler |
---|
627 | ); |
---|
628 | |
---|
629 | /* |
---|
630 | * _CPU_ISR_install_vector |
---|
631 | * |
---|
632 | * This routine installs an interrupt vector. |
---|
633 | */ |
---|
634 | |
---|
635 | void _CPU_ISR_install_vector( |
---|
636 | uint32_t vector, |
---|
637 | proc_ptr new_handler, |
---|
638 | proc_ptr *old_handler |
---|
639 | ); |
---|
640 | |
---|
641 | /* |
---|
642 | * _CPU_Install_interrupt_stack |
---|
643 | * |
---|
644 | * This routine installs the hardware interrupt stack pointer. |
---|
645 | * |
---|
646 | * NOTE: It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
647 | * is TRUE. |
---|
648 | */ |
---|
649 | |
---|
650 | void _CPU_Install_interrupt_stack( void ); |
---|
651 | |
---|
652 | /* |
---|
653 | * _CPU_Thread_Idle_body |
---|
654 | * |
---|
655 | * This routine is the CPU dependent IDLE thread body. |
---|
656 | * |
---|
657 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
---|
658 | * is TRUE. |
---|
659 | */ |
---|
660 | |
---|
661 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
---|
662 | |
---|
663 | /* |
---|
664 | * _CPU_Context_switch |
---|
665 | * |
---|
666 | * This routine switches from the run context to the heir context. |
---|
667 | */ |
---|
668 | |
---|
669 | void _CPU_Context_switch( |
---|
670 | Context_Control *run, |
---|
671 | Context_Control *heir |
---|
672 | ); |
---|
673 | |
---|
674 | /* |
---|
675 | * _CPU_Context_restore |
---|
676 | * |
---|
677 | * This routine is generally used only to restart self in an |
---|
678 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
679 | */ |
---|
680 | |
---|
681 | void _CPU_Context_restore( |
---|
682 | Context_Control *new_context |
---|
683 | ) RTEMS_NO_RETURN; |
---|
684 | |
---|
685 | /* |
---|
686 | * @brief This routine saves the floating point context passed to it. |
---|
687 | * |
---|
688 | * _CPU_Context_save_fp |
---|
689 | * |
---|
690 | */ |
---|
691 | void _CPU_Context_save_fp( |
---|
692 | Context_Control_fp **fp_context_ptr |
---|
693 | ); |
---|
694 | |
---|
695 | /* |
---|
696 | * @brief This routine restores the floating point context passed to it. |
---|
697 | * |
---|
698 | * _CPU_Context_restore_fp |
---|
699 | * |
---|
700 | */ |
---|
701 | void _CPU_Context_restore_fp( |
---|
702 | Context_Control_fp **fp_context_ptr |
---|
703 | ); |
---|
704 | |
---|
705 | static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) |
---|
706 | { |
---|
707 | /* TODO */ |
---|
708 | } |
---|
709 | |
---|
710 | static inline void _CPU_Context_validate( uintptr_t pattern ) |
---|
711 | { |
---|
712 | while (1) { |
---|
713 | /* TODO */ |
---|
714 | } |
---|
715 | } |
---|
716 | |
---|
717 | /* FIXME */ |
---|
718 | typedef CPU_Interrupt_frame CPU_Exception_frame; |
---|
719 | |
---|
720 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
721 | |
---|
722 | typedef uint32_t CPU_Counter_ticks; |
---|
723 | |
---|
724 | CPU_Counter_ticks _CPU_Counter_read( void ); |
---|
725 | |
---|
726 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
---|
727 | CPU_Counter_ticks second, |
---|
728 | CPU_Counter_ticks first |
---|
729 | ) |
---|
730 | { |
---|
731 | return second - first; |
---|
732 | } |
---|
733 | |
---|
734 | #ifdef __cplusplus |
---|
735 | } |
---|
736 | #endif |
---|
737 | |
---|
738 | #endif |
---|