1 | /** |
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2 | * @file |
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3 | */ |
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4 | |
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5 | /* |
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6 | * This include file contains information pertaining to the Hitachi SH |
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7 | * processor. |
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8 | * |
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9 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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10 | * Bernd Becker (becker@faw.uni-ulm.de) |
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11 | * |
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12 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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13 | * |
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14 | * This program is distributed in the hope that it will be useful, |
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15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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17 | * |
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18 | * |
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19 | * COPYRIGHT (c) 1998-2006. |
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20 | * On-Line Applications Research Corporation (OAR). |
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21 | * |
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22 | * The license and distribution terms for this file may be |
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23 | * found in the file LICENSE in this distribution or at |
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24 | * http://www.rtems.org/license/LICENSE. |
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25 | */ |
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26 | |
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27 | #ifndef _RTEMS_SCORE_CPU_H |
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28 | #define _RTEMS_SCORE_CPU_H |
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29 | |
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30 | #ifdef __cplusplus |
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31 | extern "C" { |
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32 | #endif |
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33 | |
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34 | #include <rtems/score/basedefs.h> |
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35 | #include <rtems/score/sh.h> |
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36 | |
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37 | /* conditional compilation parameters */ |
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38 | |
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39 | /* |
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40 | * Does the CPU follow the simple vectored interrupt model? |
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41 | * |
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42 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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43 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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44 | * table |
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45 | * |
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46 | * SH Specific Information: |
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47 | * |
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48 | * XXX document implementation including references if appropriate |
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49 | */ |
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50 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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51 | |
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52 | /* |
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53 | * Does the RTEMS invoke the user's ISR with the vector number and |
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54 | * a pointer to the saved interrupt frame (1) or just the vector |
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55 | * number (0)? |
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56 | */ |
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57 | |
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58 | #define CPU_ISR_PASSES_FRAME_POINTER FALSE |
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59 | |
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60 | /* |
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61 | * Does the CPU have hardware floating point? |
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62 | * |
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63 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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64 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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65 | * |
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66 | * We currently support sh1 only, which has no FPU, other SHes have an FPU |
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67 | * |
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68 | * The macro name "SH_HAS_FPU" should be made CPU specific. |
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69 | * It indicates whether or not this CPU model has FP support. For |
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70 | * example, it would be possible to have an i386_nofp CPU model |
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71 | * which set this to false to indicate that you have an i386 without |
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72 | * an i387 and wish to leave floating point support out of RTEMS. |
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73 | */ |
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74 | |
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75 | #if SH_HAS_FPU |
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76 | #define CPU_HARDWARE_FP TRUE |
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77 | #define CPU_SOFTWARE_FP FALSE |
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78 | #else |
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79 | #define CPU_SOFTWARE_FP FALSE |
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80 | #define CPU_HARDWARE_FP FALSE |
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81 | #endif |
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82 | |
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83 | /* |
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84 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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85 | * |
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86 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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87 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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88 | * |
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89 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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90 | */ |
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91 | |
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92 | #if SH_HAS_FPU |
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93 | #define CPU_ALL_TASKS_ARE_FP TRUE |
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94 | #else |
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95 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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96 | #endif |
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97 | |
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98 | /* |
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99 | * Should the IDLE task have a floating point context? |
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100 | * |
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101 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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102 | * and it has a floating point context which is switched in and out. |
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103 | * If FALSE, then the IDLE task does not have a floating point context. |
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104 | * |
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105 | * Setting this to TRUE negatively impacts the time required to preempt |
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106 | * the IDLE task from an interrupt because the floating point context |
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107 | * must be saved as part of the preemption. |
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108 | */ |
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109 | |
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110 | #if SH_HAS_FPU |
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111 | #define CPU_IDLE_TASK_IS_FP TRUE |
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112 | #else |
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113 | #define CPU_IDLE_TASK_IS_FP FALSE |
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114 | #endif |
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115 | |
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116 | /* |
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117 | * Should the saving of the floating point registers be deferred |
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118 | * until a context switch is made to another different floating point |
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119 | * task? |
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120 | * |
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121 | * If TRUE, then the floating point context will not be stored until |
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122 | * necessary. It will remain in the floating point registers and not |
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123 | * disturned until another floating point task is switched to. |
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124 | * |
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125 | * If FALSE, then the floating point context is saved when a floating |
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126 | * point task is switched out and restored when the next floating point |
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127 | * task is restored. The state of the floating point registers between |
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128 | * those two operations is not specified. |
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129 | * |
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130 | * If the floating point context does NOT have to be saved as part of |
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131 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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132 | * |
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133 | * Setting this flag to TRUE results in using a different algorithm |
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134 | * for deciding when to save and restore the floating point context. |
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135 | * The deferred FP switch algorithm minimizes the number of times |
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136 | * the FP context is saved and restored. The FP context is not saved |
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137 | * until a context switch is made to another, different FP task. |
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138 | * Thus in a system with only one FP task, the FP context will never |
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139 | * be saved or restored. |
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140 | */ |
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141 | |
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142 | #if SH_HAS_FPU |
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143 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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144 | #else |
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145 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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146 | #endif |
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147 | |
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148 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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149 | |
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150 | /* |
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151 | * Does the stack grow up (toward higher addresses) or down |
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152 | * (toward lower addresses)? |
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153 | * |
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154 | * If TRUE, then the grows upward. |
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155 | * If FALSE, then the grows toward smaller addresses. |
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156 | */ |
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157 | |
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158 | #define CPU_STACK_GROWS_UP FALSE |
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159 | |
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160 | /* FIXME: Is this the right value? */ |
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161 | #define CPU_CACHE_LINE_BYTES 16 |
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162 | |
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163 | #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
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164 | |
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165 | /* |
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166 | * The following defines the number of bits actually used in the |
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167 | * interrupt field of the task mode. How those bits map to the |
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168 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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169 | */ |
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170 | |
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171 | #define CPU_MODES_INTERRUPT_MASK 0x0000000f |
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172 | |
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173 | #define CPU_MAXIMUM_PROCESSORS 32 |
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174 | |
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175 | /* |
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176 | * Processor defined structures required for cpukit/score. |
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177 | */ |
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178 | |
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179 | /* may need to put some structures here. */ |
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180 | |
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181 | /* |
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182 | * Contexts |
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183 | * |
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184 | * Generally there are 2 types of context to save. |
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185 | * 1. Interrupt registers to save |
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186 | * 2. Task level registers to save |
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187 | * |
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188 | * This means we have the following 3 context items: |
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189 | * 1. task level context stuff:: Context_Control |
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190 | * 2. floating point task stuff:: Context_Control_fp |
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191 | * 3. special interrupt level context :: Context_Control_interrupt |
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192 | * |
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193 | * On some processors, it is cost-effective to save only the callee |
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194 | * preserved registers during a task context switch. This means |
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195 | * that the ISR code needs to save those registers which do not |
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196 | * persist across function calls. It is not mandatory to make this |
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197 | * distinctions between the caller/callee saves registers for the |
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198 | * purpose of minimizing context saved during task switch and on interrupts. |
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199 | * If the cost of saving extra registers is minimal, simplicity is the |
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200 | * choice. Save the same context on interrupt entry as for tasks in |
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201 | * this case. |
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202 | * |
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203 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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204 | * care should be used in designing the context area. |
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205 | * |
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206 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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207 | * structure will not be used or it simply consist of an array of a |
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208 | * fixed number of bytes. This is done when the floating point context |
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209 | * is dumped by a "FP save context" type instruction and the format |
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210 | * is not really defined by the CPU. In this case, there is no need |
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211 | * to figure out the exact format -- only the size. Of course, although |
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212 | * this is enough information for RTEMS, it is probably not enough for |
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213 | * a debugger such as gdb. But that is another problem. |
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214 | */ |
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215 | |
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216 | typedef struct { |
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217 | uint32_t *r15; /* stack pointer */ |
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218 | |
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219 | uint32_t macl; |
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220 | uint32_t mach; |
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221 | uint32_t *pr; |
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222 | |
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223 | uint32_t *r14; /* frame pointer/call saved */ |
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224 | |
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225 | uint32_t r13; /* call saved */ |
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226 | uint32_t r12; /* call saved */ |
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227 | uint32_t r11; /* call saved */ |
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228 | uint32_t r10; /* call saved */ |
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229 | uint32_t r9; /* call saved */ |
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230 | uint32_t r8; /* call saved */ |
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231 | |
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232 | uint32_t *r7; /* arg in */ |
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233 | uint32_t *r6; /* arg in */ |
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234 | |
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235 | #if 0 |
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236 | uint32_t *r5; /* arg in */ |
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237 | uint32_t *r4; /* arg in */ |
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238 | #endif |
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239 | |
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240 | uint32_t *r3; /* scratch */ |
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241 | uint32_t *r2; /* scratch */ |
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242 | uint32_t *r1; /* scratch */ |
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243 | |
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244 | uint32_t *r0; /* arg return */ |
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245 | |
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246 | uint32_t gbr; |
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247 | uint32_t sr; |
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248 | |
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249 | } Context_Control; |
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250 | |
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251 | #define _CPU_Context_Get_SP( _context ) \ |
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252 | (_context)->r15 |
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253 | |
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254 | typedef struct { |
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255 | #if SH_HAS_FPU |
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256 | #ifdef SH4_USE_X_REGISTERS |
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257 | union { |
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258 | float f[16]; |
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259 | double d[8]; |
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260 | } x; |
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261 | #endif |
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262 | union { |
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263 | float f[16]; |
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264 | double d[8]; |
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265 | } r; |
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266 | float fpul; /* fp communication register */ |
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267 | uint32_t fpscr; /* fp control register */ |
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268 | #endif /* SH_HAS_FPU */ |
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269 | } Context_Control_fp; |
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270 | |
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271 | typedef struct { |
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272 | } CPU_Interrupt_frame; |
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273 | |
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274 | /* |
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275 | * This variable is optional. It is used on CPUs on which it is difficult |
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276 | * to generate an "uninitialized" FP context. It is filled in by |
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277 | * _CPU_Initialize and copied into the task's FP context area during |
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278 | * _CPU_Context_Initialize. |
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279 | */ |
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280 | |
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281 | #if SH_HAS_FPU |
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282 | extern Context_Control_fp _CPU_Null_fp_context; |
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283 | #endif |
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284 | |
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285 | /* |
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286 | * Nothing prevents the porter from declaring more CPU specific variables. |
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287 | */ |
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288 | |
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289 | /* XXX: if needed, put more variables here */ |
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290 | void CPU_delay( uint32_t microseconds ); |
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291 | |
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292 | /* |
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293 | * The size of the floating point context area. On some CPUs this |
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294 | * will not be a "sizeof" because the format of the floating point |
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295 | * area is not defined -- only the size is. This is usually on |
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296 | * CPUs with a "floating point save context" instruction. |
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297 | */ |
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298 | |
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299 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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300 | |
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301 | /* |
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302 | * Amount of extra stack (above minimum stack size) required by |
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303 | * MPCI receive server thread. Remember that in a multiprocessor |
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304 | * system this thread must exist and be able to process all directives. |
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305 | */ |
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306 | |
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307 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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308 | |
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309 | /* |
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310 | * This defines the number of entries in the ISR_Vector_table managed |
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311 | * by RTEMS. |
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312 | */ |
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313 | |
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314 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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315 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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316 | |
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317 | /* |
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318 | * This is defined if the port has a special way to report the ISR nesting |
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319 | * level. Most ports maintain the variable _ISR_Nest_level. |
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320 | */ |
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321 | |
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322 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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323 | |
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324 | /* |
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325 | * Should be large enough to run all RTEMS tests. This ensures |
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326 | * that a "reasonable" small application should not have any problems. |
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327 | * |
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328 | * We have been able to run the sptests with this value, but have not |
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329 | * been able to run the tmtest suite. |
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330 | */ |
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331 | |
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332 | #define CPU_STACK_MINIMUM_SIZE 4096 |
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333 | |
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334 | #define CPU_SIZEOF_POINTER 4 |
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335 | |
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336 | /* |
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337 | * CPU's worst alignment requirement for data types on a byte boundary. This |
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338 | * alignment does not take into account the requirements for the stack. |
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339 | */ |
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340 | #if defined(__SH4__) |
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341 | /* FIXME: sh3 and SH3E? */ |
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342 | #define CPU_ALIGNMENT 8 |
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343 | #else |
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344 | #define CPU_ALIGNMENT 4 |
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345 | #endif |
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346 | |
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347 | /* |
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348 | * This number corresponds to the byte alignment requirement for the |
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349 | * heap handler. This alignment requirement may be stricter than that |
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350 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
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351 | * common for the heap to follow the same alignment requirement as |
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352 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
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353 | * then this should be set to CPU_ALIGNMENT. |
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354 | * |
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355 | * NOTE: This does not have to be a power of 2. It does have to |
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356 | * be greater or equal to than CPU_ALIGNMENT. |
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357 | */ |
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358 | |
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359 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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360 | |
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361 | #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT |
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362 | |
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363 | #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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364 | |
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365 | /* |
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366 | * ISR handler macros |
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367 | */ |
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368 | |
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369 | /* |
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370 | * Disable all interrupts for an RTEMS critical section. The previous |
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371 | * level is returned in _level. |
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372 | */ |
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373 | |
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374 | #define _CPU_ISR_Disable( _level) \ |
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375 | sh_disable_interrupts( _level ) |
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376 | |
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377 | /* |
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378 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
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379 | * This indicates the end of an RTEMS critical section. The parameter |
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380 | * _level is not modified. |
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381 | */ |
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382 | |
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383 | #define _CPU_ISR_Enable( _level) \ |
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384 | sh_enable_interrupts( _level) |
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385 | |
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386 | /* |
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387 | * This temporarily restores the interrupt to _level before immediately |
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388 | * disabling them again. This is used to divide long RTEMS critical |
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389 | * sections into two or more parts. The parameter _level is not |
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390 | * modified. |
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391 | */ |
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392 | |
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393 | #define _CPU_ISR_Flash( _level) \ |
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394 | sh_flash_interrupts( _level) |
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395 | |
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396 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
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397 | { |
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398 | sh_get_interrupt_level( level ); |
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399 | return level == 0; |
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400 | } |
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401 | |
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402 | /* |
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403 | * Map interrupt level in task mode onto the hardware that the CPU |
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404 | * actually provides. Currently, interrupt levels which do not |
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405 | * map onto the CPU in a generic fashion are undefined. Someday, |
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406 | * it would be nice if these were "mapped" by the application |
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407 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
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408 | * 8 - 255 would be available for bsp/application specific meaning. |
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409 | * This could be used to manage a programmable interrupt controller |
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410 | * via the rtems_task_mode directive. |
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411 | */ |
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412 | |
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413 | #define _CPU_ISR_Set_level( _newlevel) \ |
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414 | sh_set_interrupt_level(_newlevel) |
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415 | |
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416 | uint32_t _CPU_ISR_Get_level( void ); |
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417 | |
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418 | /* end of ISR handler macros */ |
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419 | |
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420 | /* Context handler macros */ |
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421 | |
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422 | /* |
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423 | * Initialize the context to a state suitable for starting a |
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424 | * task after a context restore operation. Generally, this |
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425 | * involves: |
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426 | * |
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427 | * - setting a starting address |
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428 | * - preparing the stack |
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429 | * - preparing the stack and frame pointers |
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430 | * - setting the proper interrupt level in the context |
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431 | * - initializing the floating point context |
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432 | * |
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433 | * This routine generally does not set any unnecessary register |
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434 | * in the context. The state of the "general data" registers is |
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435 | * undefined at task start time. |
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436 | * |
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437 | * NOTE: This is_fp parameter is TRUE if the thread is to be a floating |
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438 | * point thread. This is typically only used on CPUs where the |
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439 | * FPU may be easily disabled by software such as on the SPARC |
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440 | * where the PSR contains an enable FPU bit. |
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441 | */ |
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442 | |
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443 | /* |
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444 | * FIXME: defined as a function for debugging - should be a macro |
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445 | */ |
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446 | void _CPU_Context_Initialize( |
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447 | Context_Control *_the_context, |
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448 | void *_stack_base, |
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449 | uint32_t _size, |
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450 | uint32_t _isr, |
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451 | void (*_entry_point)(void), |
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452 | int _is_fp, |
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453 | void *_tls_area ); |
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454 | |
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455 | /* |
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456 | * This routine is responsible for somehow restarting the currently |
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457 | * executing task. If you are lucky, then all that is necessary |
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458 | * is restoring the context. Otherwise, there will need to be |
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459 | * a special assembly routine which does something special in this |
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460 | * case. Context_Restore should work most of the time. It will |
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461 | * not work if restarting self conflicts with the stack frame |
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462 | * assumptions of restoring a context. |
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463 | */ |
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464 | |
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465 | #define _CPU_Context_Restart_self( _the_context ) \ |
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466 | _CPU_Context_restore( (_the_context) ); |
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467 | |
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468 | /* |
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469 | * This routine initializes the FP context area passed to it to. |
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470 | * There are a few standard ways in which to initialize the |
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471 | * floating point context. The code included for this macro assumes |
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472 | * that this is a CPU in which a "initial" FP context was saved into |
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473 | * _CPU_Null_fp_context and it simply copies it to the destination |
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474 | * context passed to it. |
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475 | * |
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476 | * Other models include (1) not doing anything, and (2) putting |
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477 | * a "null FP status word" in the correct place in the FP context. |
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478 | * SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have. |
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479 | */ |
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480 | |
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481 | #if SH_HAS_FPU |
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482 | #define _CPU_Context_Initialize_fp( _destination ) \ |
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483 | do { \ |
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484 | *(*(_destination)) = _CPU_Null_fp_context;\ |
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485 | } while(0) |
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486 | #else |
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487 | #define _CPU_Context_Initialize_fp( _destination ) \ |
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488 | { } |
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489 | #endif |
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490 | |
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491 | /* end of Context handler macros */ |
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492 | |
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493 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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494 | |
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495 | #define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE |
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496 | |
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497 | /* functions */ |
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498 | |
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499 | /* |
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500 | * @brief CPU Initialize |
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501 | * |
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502 | * _CPU_Initialize |
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503 | * |
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504 | * This routine performs CPU dependent initialization. |
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505 | */ |
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506 | void _CPU_Initialize(void); |
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507 | |
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508 | typedef void ( *CPU_ISR_raw_handler )( void ); |
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509 | |
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510 | extern CPU_ISR_raw_handler _Hardware_isr_Table[]; |
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511 | |
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512 | void _CPU_ISR_install_raw_handler( |
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513 | uint32_t vector, |
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514 | CPU_ISR_raw_handler new_handler, |
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515 | CPU_ISR_raw_handler *old_handler |
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516 | ); |
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517 | |
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518 | typedef void ( *CPU_ISR_handler )( uint32_t ); |
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519 | |
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520 | void _CPU_ISR_install_vector( |
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521 | uint32_t vector, |
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522 | CPU_ISR_handler new_handler, |
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523 | CPU_ISR_handler *old_handler |
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524 | ); |
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525 | |
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526 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
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527 | |
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528 | /* |
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529 | * _CPU_Context_switch |
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530 | * |
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531 | * This routine switches from the run context to the heir context. |
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532 | */ |
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533 | |
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534 | void _CPU_Context_switch( |
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535 | Context_Control *run, |
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536 | Context_Control *heir |
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537 | ); |
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538 | |
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539 | /* |
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540 | * _CPU_Context_restore |
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541 | * |
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542 | * This routine is generally used only to restart self in an |
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543 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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544 | */ |
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545 | |
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546 | RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context ); |
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547 | |
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548 | /* |
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549 | * @brief This routine saves the floating point context passed to it. |
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550 | * |
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551 | * _CPU_Context_save_fp |
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552 | * |
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553 | */ |
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554 | void _CPU_Context_save_fp( |
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555 | Context_Control_fp **fp_context_ptr |
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556 | ); |
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557 | |
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558 | /* |
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559 | * @brief This routine restores the floating point context passed to it. |
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560 | * |
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561 | * _CPU_Context_restore_fp |
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562 | * |
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563 | */ |
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564 | void _CPU_Context_restore_fp( |
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565 | Context_Control_fp **fp_context_ptr |
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566 | ); |
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567 | |
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568 | /* FIXME */ |
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569 | typedef CPU_Interrupt_frame CPU_Exception_frame; |
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570 | |
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571 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
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572 | |
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573 | typedef uint32_t CPU_Counter_ticks; |
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574 | |
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575 | uint32_t _CPU_Counter_frequency( void ); |
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576 | |
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577 | CPU_Counter_ticks _CPU_Counter_read( void ); |
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578 | |
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579 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
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580 | CPU_Counter_ticks second, |
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581 | CPU_Counter_ticks first |
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582 | ) |
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583 | { |
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584 | return second - first; |
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585 | } |
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586 | |
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587 | /** Type that can store a 32-bit integer or a pointer. */ |
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588 | typedef uintptr_t CPU_Uint32ptr; |
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589 | |
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590 | /** Types related to SH specific ISRs */ |
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591 | typedef void sh_isr; |
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592 | typedef void ( *sh_isr_entry )( void ); |
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593 | |
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594 | #ifdef __cplusplus |
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595 | } |
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596 | #endif |
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597 | |
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598 | #endif |
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