source: rtems/cpukit/score/cpu/sh/cpu.c @ fce900b5

5
Last change on this file since fce900b5 was ec5d7f92, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 7, 2016 at 8:09:01 PM

score: Delete dead copy and paste code

  • Property mode set to 100644
File size: 5.0 KB
Line 
1/**
2 * @file
3 *
4 * @brief SuperH CPU Support
5 *
6 * This file contains information pertaining to the Hitachi SH
7 * processor.
8 */
9
10/*
11 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
12 *           Bernd Becker (becker@faw.uni-ulm.de)
13 *
14 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
15 *
16 *  This program is distributed in the hope that it will be useful,
17 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 *
20 *
21 *  COPYRIGHT (c) 1998-2001.
22 *  On-Line Applications Research Corporation (OAR).
23 *
24 *  The license and distribution terms for this file may be
25 *  found in the file LICENSE in this distribution or at
26 *  http://www.rtems.org/license/LICENSE.
27 */
28
29#ifdef HAVE_CONFIG_H
30#include "config.h"
31#endif
32
33#include <rtems/system.h>
34#include <rtems/score/isr.h>
35#include <rtems/score/sh_io.h>
36#include <rtems/score/cpu.h>
37#include <rtems/score/sh.h>
38
39/* referenced in start.S */
40extern proc_ptr vectab[] ;
41
42proc_ptr vectab[256] ;
43
44extern proc_ptr _Hardware_isr_Table[];
45
46#if SH_HAS_FPU
47Context_Control_fp _CPU_Null_fp_context;
48#endif
49
50/*  _CPU_Initialize
51 *
52 *  This routine performs processor dependent initialization.
53 *
54 *  INPUT PARAMETERS: NONE
55 */
56
57void _CPU_Initialize(void)
58{
59  register uint32_t   level = 0;
60
61  /*
62   *  If there is not an easy way to initialize the FP context
63   *  during Context_Initialize, then it is usually easier to
64   *  save an "uninitialized" FP context here and copy it to
65   *  the task's during Context_Initialize.
66   */
67
68  /* FP context initialization support goes here */
69#if SH_HAS_FPU
70  /* FIXME: When not to use SH4_FPSCR_PR ? */
71#ifdef __SH4__
72  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR;
73#endif
74#ifdef __SH3E__
75  /* FIXME: Wild guess :) */
76  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM;
77#endif
78#endif
79
80  /* enable interrupts */
81  _CPU_ISR_Set_level( level ) ;
82}
83
84/*
85 *  _CPU_ISR_Get_level
86 */
87
88uint32_t   _CPU_ISR_Get_level( void )
89{
90  /*
91   *  This routine returns the current interrupt level.
92   */
93
94  register uint32_t   _mask ;
95
96  sh_get_interrupt_level( _mask );
97
98  return ( _mask);
99}
100
101/*
102 *  _CPU_ISR_install_raw_handler
103 */
104
105void _CPU_ISR_install_raw_handler(
106  uint32_t    vector,
107  proc_ptr    new_handler,
108  proc_ptr   *old_handler
109)
110{
111  /*
112   *  This is where we install the interrupt handler into the "raw" interrupt
113   *  table used by the CPU to dispatch interrupt handlers.
114   */
115  volatile proc_ptr     *vbr ;
116
117#if SH_PARANOID_ISR
118  uint32_t              level ;
119
120  sh_disable_interrupts( level );
121#endif
122
123  /* get vbr */
124  __asm__ ( "stc vbr,%0" : "=r" (vbr) );
125
126  *old_handler = vbr[vector] ;
127  vbr[vector]  = new_handler ;
128
129#if SH_PARANOID_ISR
130  sh_enable_interrupts( level );
131#endif
132}
133
134
135/*
136 *  _CPU_ISR_install_vector
137 *
138 *  This kernel routine installs the RTEMS handler for the
139 *  specified vector.
140 *
141 *  Input parameters:
142 *    vector      - interrupt vector number
143 *    old_handler - former ISR for this vector number
144 *    new_handler - replacement ISR for this vector number
145 *
146 *  Output parameters:  NONE
147 *
148 */
149
150void _CPU_ISR_install_vector(
151  uint32_t    vector,
152  proc_ptr    new_handler,
153  proc_ptr   *old_handler
154)
155{
156#if defined(__sh1__) || defined(__sh2__)
157   proc_ptr ignored ;
158#endif
159   *old_handler = _ISR_Vector_table[ vector ];
160
161 /*
162  *  If the interrupt vector table is a table of pointer to isr entry
163  *  points, then we need to install the appropriate RTEMS interrupt
164  *  handler for this vector number.
165  */
166#if defined(__sh1__) || defined(__sh2__)
167  _CPU_ISR_install_raw_handler(vector, _Hardware_isr_Table[vector], &ignored );
168#endif
169
170 /*
171  *  We put the actual user ISR address in '_ISR_Vector_table'.
172  *  This will be used by __ISR_Handler so the user gets control.
173  */
174
175 _ISR_Vector_table[ vector ] = new_handler;
176}
177
178/*
179 *  _CPU_Thread_Idle_body
180 *
181 *  NOTES:
182 *
183 *  1. This is the same as the regular CPU independent algorithm.
184 *
185 *  2. If you implement this using a "halt", "idle", or "shutdown"
186 *     instruction, then don't forget to put it in an infinite loop.
187 *
188 *  3. Be warned. Some processors with onboard DMA have been known
189 *     to stop the DMA if the CPU were put in IDLE mode.  This might
190 *     also be a problem with other on-chip peripherals.  So use this
191 *     hook with caution.
192 */
193
194#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
195void *_CPU_Thread_Idle_body( uintptr_t ignored )
196{
197
198  for( ; ; )
199    {
200      __asm__ volatile("nop");
201    }
202    /* insert your "halt" instruction here */ ;
203}
204#endif
205
206void _CPU_Context_Initialize(
207  Context_Control       *_the_context,
208  void                  *_stack_base,
209  uint32_t              _size,
210  uint32_t              _isr,
211  void  (*_entry_point)(void),
212  int                   _is_fp,
213  void                  *_tls_base)
214{
215  _the_context->r15 = (uint32_t *) ((uint32_t) (_stack_base) + (_size) );
216#if defined(__sh1__) || defined(__sh2__) || defined(__SH2E__)
217  _the_context->sr  = (_isr << 4) & 0x00f0 ;
218#else
219  _the_context->sr  = SH4_SR_MD | ((_isr << 4) & 0x00f0);
220#endif
221  _the_context->pr  = (uint32_t *) _entry_point ;
222
223
224#if 0 && SH_HAS_FPU
225   /* Disable FPU if it is non-fp task */
226  if(!_is_fp)
227    _the_context->sr |= SH4_SR_FD;
228#endif
229}
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