source: rtems/cpukit/score/cpu/sh/cpu.c @ d0279f6e

4.9
Last change on this file since d0279f6e was df4fcaa, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 8, 2008 at 3:19:23 PM

2008-09-08 Joel Sherrill <joel.sherrill@…>

  • cpu.c: Remove extraneous spaces.
  • Property mode set to 100644
File size: 5.7 KB
Line 
1/*
2 *  This file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 *           Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 *  This program is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 *  COPYRIGHT (c) 1998-2001.
16 *  On-Line Applications Research Corporation (OAR).
17 *
18 *  The license and distribution terms for this file may be
19 *  found in the file LICENSE in this distribution or at
20 *  http://www.rtems.com/license/LICENSE.
21 *
22 *  $Id$
23 */
24 
25#include <rtems/system.h>
26#include <rtems/score/isr.h>
27#include <rtems/score/sh_io.h>
28#include <rtems/score/cpu.h>
29#include <rtems/score/sh.h>
30
31/* referenced in start.S */
32extern proc_ptr vectab[] ;
33
34proc_ptr vectab[256] ;
35
36extern proc_ptr _Hardware_isr_Table[];
37
38/*  _CPU_Initialize
39 *
40 *  This routine performs processor dependent initialization.
41 *
42 *  INPUT PARAMETERS:
43 *    thread_dispatch - address of disptaching routine
44 */
45
46
47void _CPU_Initialize(
48  void      (*thread_dispatch)      /* ignored on this CPU */
49)
50{
51  register uint32_t   level = 0;
52
53  /*
54   *  The thread_dispatch argument is the address of the entry point
55   *  for the routine called at the end of an ISR once it has been
56   *  decided a context switch is necessary.  On some compilation
57   *  systems it is difficult to call a high-level language routine
58   *  from assembly.  This allows us to trick these systems.
59   *
60   *  If you encounter this problem save the entry point in a CPU
61   *  dependent variable.
62   */
63
64  _CPU_Thread_dispatch_pointer = thread_dispatch;
65
66  /*
67   *  If there is not an easy way to initialize the FP context
68   *  during Context_Initialize, then it is usually easier to
69   *  save an "uninitialized" FP context here and copy it to
70   *  the task's during Context_Initialize.
71   */
72
73  /* FP context initialization support goes here */
74  /* FIXME: When not to use SH4_FPSCR_PR ? */
75#ifdef __SH4__
76  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR;
77#endif
78#ifdef __SH3E__
79  /* FIXME: Wild guess :) */
80  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM;
81#endif
82
83  /* enable interrupts */
84  _CPU_ISR_Set_level( level ) ;
85}
86
87/*PAGE
88 *
89 *  _CPU_ISR_Get_level
90 */
91 
92uint32_t   _CPU_ISR_Get_level( void )
93{
94  /*
95   *  This routine returns the current interrupt level.
96   */
97
98  register uint32_t   _mask ;
99 
100  sh_get_interrupt_level( _mask );
101 
102  return ( _mask);
103}
104
105/*PAGE
106 *
107 *  _CPU_ISR_install_raw_handler
108 */
109 
110void _CPU_ISR_install_raw_handler(
111  uint32_t    vector,
112  proc_ptr    new_handler,
113  proc_ptr   *old_handler
114)
115{
116  /*
117   *  This is where we install the interrupt handler into the "raw" interrupt
118   *  table used by the CPU to dispatch interrupt handlers.
119   */
120  volatile proc_ptr     *vbr ;
121
122#if SH_PARANOID_ISR 
123  uint32_t              level ;
124
125  sh_disable_interrupts( level );
126#endif   
127
128  /* get vbr */
129  asm ( "stc vbr,%0" : "=r" (vbr) );
130
131  *old_handler = vbr[vector] ;
132  vbr[vector]  = new_handler ;
133
134#if SH_PARANOID_ISR
135  sh_enable_interrupts( level );
136#endif
137}
138
139
140/*PAGE
141 *
142 *  _CPU_ISR_install_vector
143 *
144 *  This kernel routine installs the RTEMS handler for the
145 *  specified vector.
146 *
147 *  Input parameters:
148 *    vector      - interrupt vector number
149 *    old_handler - former ISR for this vector number
150 *    new_handler - replacement ISR for this vector number
151 *
152 *  Output parameters:  NONE
153 *
154 */
155
156#if defined(__sh1__) || defined(__sh2__)
157void _CPU_ISR_install_vector(
158  uint32_t    vector,
159  proc_ptr    new_handler,
160  proc_ptr   *old_handler
161)
162{
163   proc_ptr ignored ;
164#if 0 
165   if(( vector <= 113) && ( vector >= 11))
166     {
167#endif
168       *old_handler = _ISR_Vector_table[ vector ];
169
170       /*
171        *  If the interrupt vector table is a table of pointer to isr entry
172        *  points, then we need to install the appropriate RTEMS interrupt
173        *  handler for this vector number.
174        */
175       _CPU_ISR_install_raw_handler(vector, 
176                                    _Hardware_isr_Table[vector],
177                                    &ignored );
178
179       /*
180        *  We put the actual user ISR address in '_ISR_Vector_table'. 
181        *  This will be used by __ISR_Handler so the user gets control.
182        */
183
184       _ISR_Vector_table[ vector ] = new_handler;
185#if 0
186     }
187#endif
188}
189#endif /* _CPU_ISR_install_vector */
190
191/*PAGE
192 *
193 *  _CPU_Thread_Idle_body
194 *
195 *  NOTES:
196 *
197 *  1. This is the same as the regular CPU independent algorithm.
198 *
199 *  2. If you implement this using a "halt", "idle", or "shutdown"
200 *     instruction, then don't forget to put it in an infinite loop.
201 *
202 *  3. Be warned. Some processors with onboard DMA have been known
203 *     to stop the DMA if the CPU were put in IDLE mode.  This might
204 *     also be a problem with other on-chip peripherals.  So use this
205 *     hook with caution.
206 */
207
208#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
209void *_CPU_Thread_Idle_body( uint32_t ignored )
210{
211
212  for( ; ; )
213    {
214      asm volatile("nop");
215    }
216    /* insert your "halt" instruction here */ ;
217}
218#endif
219
220#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
221
222uint8_t   _bit_set_table[16] = 
223  { 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0};
224
225
226#endif
227
228void _CPU_Context_Initialize(
229  Context_Control       *_the_context,
230  void                  *_stack_base,
231  uint32_t              _size,
232  uint32_t              _isr,
233  void  (*_entry_point)(void),
234  int                   _is_fp )
235{
236  _the_context->r15 = (uint32_t *) ((uint32_t) (_stack_base) + (_size) );
237#if defined(__sh1__) || defined(__sh2__) || defined(__SH2E__)
238  _the_context->sr  = (_isr << 4) & 0x00f0 ;
239#else
240  _the_context->sr  = SH4_SR_MD | ((_isr << 4) & 0x00f0);
241#endif
242  _the_context->pr  = (uint32_t *) _entry_point ;
243
244
245#if 0 && SH_HAS_FPU
246   /* Disable FPU if it is non-fp task */
247  if(!_is_fp)
248    _the_context->sr |= SH4_SR_FD;
249#endif
250}
Note: See TracBrowser for help on using the repository browser.