1 | /* |
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2 | * This file contains information pertaining to the Hitachi SH |
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3 | * processor. |
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4 | * |
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5 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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6 | * Bernd Becker (becker@faw.uni-ulm.de) |
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7 | * |
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8 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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9 | * |
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10 | * This program is distributed in the hope that it will be useful, |
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11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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13 | * |
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14 | * |
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15 | * COPYRIGHT (c) 1998-2001. |
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16 | * On-Line Applications Research Corporation (OAR). |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.com/license/LICENSE. |
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21 | * |
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22 | * $Id$ |
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23 | */ |
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24 | |
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25 | #include <rtems/system.h> |
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26 | #include <rtems/score/isr.h> |
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27 | #include <rtems/score/sh_io.h> |
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28 | #include <rtems/score/cpu.h> |
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29 | #include <rtems/score/sh.h> |
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30 | |
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31 | /* referenced in start.S */ |
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32 | extern proc_ptr vectab[] ; |
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33 | |
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34 | proc_ptr vectab[256] ; |
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35 | |
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36 | extern proc_ptr _Hardware_isr_Table[]; |
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37 | |
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38 | /* _CPU_Initialize |
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39 | * |
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40 | * This routine performs processor dependent initialization. |
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41 | * |
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42 | * INPUT PARAMETERS: NONE |
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43 | */ |
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44 | |
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45 | void _CPU_Initialize(void) |
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46 | { |
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47 | register uint32_t level = 0; |
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48 | |
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49 | /* |
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50 | * If there is not an easy way to initialize the FP context |
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51 | * during Context_Initialize, then it is usually easier to |
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52 | * save an "uninitialized" FP context here and copy it to |
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53 | * the task's during Context_Initialize. |
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54 | */ |
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55 | |
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56 | /* FP context initialization support goes here */ |
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57 | /* FIXME: When not to use SH4_FPSCR_PR ? */ |
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58 | #ifdef __SH4__ |
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59 | _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR; |
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60 | #endif |
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61 | #ifdef __SH3E__ |
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62 | /* FIXME: Wild guess :) */ |
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63 | _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM; |
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64 | #endif |
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65 | |
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66 | /* enable interrupts */ |
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67 | _CPU_ISR_Set_level( level ) ; |
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68 | } |
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69 | |
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70 | /*PAGE |
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71 | * |
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72 | * _CPU_ISR_Get_level |
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73 | */ |
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74 | |
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75 | uint32_t _CPU_ISR_Get_level( void ) |
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76 | { |
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77 | /* |
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78 | * This routine returns the current interrupt level. |
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79 | */ |
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80 | |
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81 | register uint32_t _mask ; |
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82 | |
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83 | sh_get_interrupt_level( _mask ); |
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84 | |
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85 | return ( _mask); |
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86 | } |
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87 | |
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88 | /*PAGE |
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89 | * |
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90 | * _CPU_ISR_install_raw_handler |
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91 | */ |
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92 | |
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93 | void _CPU_ISR_install_raw_handler( |
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94 | uint32_t vector, |
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95 | proc_ptr new_handler, |
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96 | proc_ptr *old_handler |
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97 | ) |
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98 | { |
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99 | /* |
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100 | * This is where we install the interrupt handler into the "raw" interrupt |
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101 | * table used by the CPU to dispatch interrupt handlers. |
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102 | */ |
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103 | volatile proc_ptr *vbr ; |
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104 | |
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105 | #if SH_PARANOID_ISR |
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106 | uint32_t level ; |
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107 | |
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108 | sh_disable_interrupts( level ); |
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109 | #endif |
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110 | |
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111 | /* get vbr */ |
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112 | asm ( "stc vbr,%0" : "=r" (vbr) ); |
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113 | |
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114 | *old_handler = vbr[vector] ; |
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115 | vbr[vector] = new_handler ; |
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116 | |
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117 | #if SH_PARANOID_ISR |
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118 | sh_enable_interrupts( level ); |
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119 | #endif |
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120 | } |
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121 | |
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122 | |
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123 | /*PAGE |
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124 | * |
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125 | * _CPU_ISR_install_vector |
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126 | * |
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127 | * This kernel routine installs the RTEMS handler for the |
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128 | * specified vector. |
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129 | * |
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130 | * Input parameters: |
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131 | * vector - interrupt vector number |
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132 | * old_handler - former ISR for this vector number |
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133 | * new_handler - replacement ISR for this vector number |
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134 | * |
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135 | * Output parameters: NONE |
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136 | * |
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137 | */ |
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138 | |
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139 | void _CPU_ISR_install_vector( |
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140 | uint32_t vector, |
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141 | proc_ptr new_handler, |
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142 | proc_ptr *old_handler |
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143 | ) |
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144 | { |
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145 | proc_ptr ignored ; |
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146 | *old_handler = _ISR_Vector_table[ vector ]; |
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147 | |
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148 | /* |
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149 | * If the interrupt vector table is a table of pointer to isr entry |
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150 | * points, then we need to install the appropriate RTEMS interrupt |
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151 | * handler for this vector number. |
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152 | */ |
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153 | #if defined(__sh1__) || defined(__sh2__) |
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154 | _CPU_ISR_install_raw_handler(vector, _Hardware_isr_Table[vector], &ignored ); |
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155 | #endif |
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156 | |
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157 | /* |
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158 | * We put the actual user ISR address in '_ISR_Vector_table'. |
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159 | * This will be used by __ISR_Handler so the user gets control. |
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160 | */ |
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161 | |
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162 | _ISR_Vector_table[ vector ] = new_handler; |
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163 | } |
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164 | |
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165 | /*PAGE |
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166 | * |
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167 | * _CPU_Thread_Idle_body |
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168 | * |
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169 | * NOTES: |
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170 | * |
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171 | * 1. This is the same as the regular CPU independent algorithm. |
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172 | * |
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173 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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174 | * instruction, then don't forget to put it in an infinite loop. |
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175 | * |
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176 | * 3. Be warned. Some processors with onboard DMA have been known |
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177 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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178 | * also be a problem with other on-chip peripherals. So use this |
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179 | * hook with caution. |
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180 | */ |
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181 | |
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182 | #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) |
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183 | void *_CPU_Thread_Idle_body( uint32_t ignored ) |
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184 | { |
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185 | |
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186 | for( ; ; ) |
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187 | { |
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188 | asm volatile("nop"); |
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189 | } |
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190 | /* insert your "halt" instruction here */ ; |
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191 | } |
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192 | #endif |
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193 | |
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194 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
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195 | |
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196 | uint8_t _bit_set_table[16] = |
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197 | { 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0}; |
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198 | |
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199 | |
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200 | #endif |
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201 | |
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202 | void _CPU_Context_Initialize( |
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203 | Context_Control *_the_context, |
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204 | void *_stack_base, |
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205 | uint32_t _size, |
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206 | uint32_t _isr, |
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207 | void (*_entry_point)(void), |
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208 | int _is_fp ) |
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209 | { |
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210 | _the_context->r15 = (uint32_t *) ((uint32_t) (_stack_base) + (_size) ); |
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211 | #if defined(__sh1__) || defined(__sh2__) || defined(__SH2E__) |
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212 | _the_context->sr = (_isr << 4) & 0x00f0 ; |
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213 | #else |
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214 | _the_context->sr = SH4_SR_MD | ((_isr << 4) & 0x00f0); |
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215 | #endif |
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216 | _the_context->pr = (uint32_t *) _entry_point ; |
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217 | |
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218 | |
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219 | #if 0 && SH_HAS_FPU |
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220 | /* Disable FPU if it is non-fp task */ |
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221 | if(!_is_fp) |
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222 | _the_context->sr |= SH4_SR_FD; |
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223 | #endif |
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224 | } |
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