source: rtems/cpukit/score/cpu/sh/cpu.c @ b72e847b

4.8
Last change on this file since b72e847b was 60f016f, checked in by Joel Sherrill <joel.sherrill@…>, on May 22, 2007 at 8:57:34 PM

2007-05-22 Joel Sherrill <joel.sherrill@…>

  • score/cpu/arm/cpu.c, score/cpu/avr/cpu.c, score/cpu/bfin/cpu.c, score/cpu/c4x/cpu.c, score/cpu/h8300/cpu.c, score/cpu/i386/cpu.c, score/cpu/m68k/cpu.c, score/cpu/mips/cpu.c, score/cpu/nios2/cpu.c, score/cpu/no_cpu/cpu.c, score/cpu/sh/cpu.c, score/cpu/sparc/cpu.c, cpukit/sapi/src/exinit.c: Move copying of CPU Table to shared executive initialization.
  • Property mode set to 100644
File size: 5.8 KB
Line 
1/*
2 *  This file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 *           Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 *  This program is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 *  COPYRIGHT (c) 1998-2001.
16 *  On-Line Applications Research Corporation (OAR).
17 *
18 *  The license and distribution terms for this file may be
19 *  found in the file LICENSE in this distribution or at
20 *  http://www.rtems.com/license/LICENSE.
21 *
22 *  $Id$
23 */
24 
25#include <rtems/system.h>
26#include <rtems/score/isr.h>
27#include <rtems/score/sh_io.h>
28#include <rtems/score/cpu.h>
29#include <rtems/score/sh.h>
30
31/* referenced in start.S */
32extern proc_ptr vectab[] ;
33
34proc_ptr vectab[256] ;
35
36extern proc_ptr _Hardware_isr_Table[];
37
38/*  _CPU_Initialize
39 *
40 *  This routine performs processor dependent initialization.
41 *
42 *  INPUT PARAMETERS:
43 *    cpu_table       - CPU table to initialize
44 *    thread_dispatch - address of disptaching routine
45 */
46
47
48void _CPU_Initialize(
49  rtems_cpu_table  *cpu_table,
50  void      (*thread_dispatch)      /* ignored on this CPU */
51)
52{
53  register uint32_t   level = 0;
54
55  /*
56   *  The thread_dispatch argument is the address of the entry point
57   *  for the routine called at the end of an ISR once it has been
58   *  decided a context switch is necessary.  On some compilation
59   *  systems it is difficult to call a high-level language routine
60   *  from assembly.  This allows us to trick these systems.
61   *
62   *  If you encounter this problem save the entry point in a CPU
63   *  dependent variable.
64   */
65
66  _CPU_Thread_dispatch_pointer = thread_dispatch;
67
68  /*
69   *  If there is not an easy way to initialize the FP context
70   *  during Context_Initialize, then it is usually easier to
71   *  save an "uninitialized" FP context here and copy it to
72   *  the task's during Context_Initialize.
73   */
74
75  /* FP context initialization support goes here */
76  /* FIXME: When not to use SH4_FPSCR_PR ? */
77#ifdef __SH4__
78  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR;
79#endif
80#ifdef __SH3E__
81  /* FIXME: Wild guess :) */
82  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM;
83#endif
84
85  /* enable interrupts */
86  _CPU_ISR_Set_level( level ) ;
87}
88
89/*PAGE
90 *
91 *  _CPU_ISR_Get_level
92 */
93 
94uint32_t   _CPU_ISR_Get_level( void )
95{
96  /*
97   *  This routine returns the current interrupt level.
98   */
99
100  register uint32_t   _mask ;
101 
102  sh_get_interrupt_level( _mask );
103 
104  return ( _mask);
105}
106
107/*PAGE
108 *
109 *  _CPU_ISR_install_raw_handler
110 */
111 
112void _CPU_ISR_install_raw_handler(
113  uint32_t    vector,
114  proc_ptr    new_handler,
115  proc_ptr   *old_handler
116)
117{
118  /*
119   *  This is where we install the interrupt handler into the "raw" interrupt
120   *  table used by the CPU to dispatch interrupt handlers.
121   */
122  volatile proc_ptr     *vbr ;
123
124#if SH_PARANOID_ISR 
125  uint32_t              level ;
126
127  sh_disable_interrupts( level );
128#endif   
129
130  /* get vbr */
131  asm ( "stc vbr,%0" : "=r" (vbr) );
132
133  *old_handler = vbr[vector] ;
134  vbr[vector]  = new_handler ;
135
136#if SH_PARANOID_ISR
137  sh_enable_interrupts( level );
138#endif
139}
140
141
142/*PAGE
143 *
144 *  _CPU_ISR_install_vector
145 *
146 *  This kernel routine installs the RTEMS handler for the
147 *  specified vector.
148 *
149 *  Input parameters:
150 *    vector      - interrupt vector number
151 *    old_handler - former ISR for this vector number
152 *    new_handler - replacement ISR for this vector number
153 *
154 *  Output parameters:  NONE
155 *
156 */
157
158#if defined(__sh1__) || defined(__sh2__)
159void _CPU_ISR_install_vector(
160  uint32_t    vector,
161  proc_ptr    new_handler,
162  proc_ptr   *old_handler
163)
164{
165   proc_ptr ignored ;
166#if 0 
167   if(( vector <= 113) && ( vector >= 11))
168     {
169#endif
170       *old_handler = _ISR_Vector_table[ vector ];
171
172       /*
173        *  If the interrupt vector table is a table of pointer to isr entry
174        *  points, then we need to install the appropriate RTEMS interrupt
175        *  handler for this vector number.
176        */
177       _CPU_ISR_install_raw_handler(vector, 
178                                    _Hardware_isr_Table[vector],
179                                    &ignored );
180
181       /*
182        *  We put the actual user ISR address in '_ISR_Vector_table'. 
183        *  This will be used by __ISR_Handler so the user gets control.
184        */
185
186       _ISR_Vector_table[ vector ] = new_handler;
187#if 0
188     }
189#endif
190}
191#endif /* _CPU_ISR_install_vector */
192
193/*PAGE
194 *
195 *  _CPU_Thread_Idle_body
196 *
197 *  NOTES:
198 *
199 *  1. This is the same as the regular CPU independent algorithm.
200 *
201 *  2. If you implement this using a "halt", "idle", or "shutdown"
202 *     instruction, then don't forget to put it in an infinite loop.
203 *
204 *  3. Be warned. Some processors with onboard DMA have been known
205 *     to stop the DMA if the CPU were put in IDLE mode.  This might
206 *     also be a problem with other on-chip peripherals.  So use this
207 *     hook with caution.
208 */
209
210#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
211void _CPU_Thread_Idle_body( void )
212{
213
214  for( ; ; )
215    {
216      asm volatile("nop");
217    }
218    /* insert your "halt" instruction here */ ;
219}
220#endif
221
222#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
223
224uint8_t   _bit_set_table[16] = 
225  { 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0};
226
227
228#endif
229
230void _CPU_Context_Initialize(
231  Context_Control       *_the_context,
232  void                  *_stack_base,
233  uint32_t              _size,
234  uint32_t              _isr,
235  void  (*_entry_point)(void),
236  int                   _is_fp )
237{
238  _the_context->r15 = (uint32_t  *) ((uint32_t  ) (_stack_base) + (_size) );
239#if defined(__sh1__) || defined(__sh2__) || defined(__SH2E__)
240  _the_context->sr  = (_isr << 4) & 0x00f0 ;
241#else
242  _the_context->sr  = SH4_SR_MD | ((_isr << 4) & 0x00f0);
243#endif
244  _the_context->pr  = (uint32_t  *) _entry_point ;
245
246
247#if 0 && SH_HAS_FPU
248   /* Disable FPU if it is non-fp task */
249  if(!_is_fp)
250    _the_context->sr |= SH4_SR_FD;
251#endif
252}
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