source: rtems/cpukit/score/cpu/sh/cpu.c @ 5bb38e15

4.104.11
Last change on this file since 5bb38e15 was 5bb38e15, checked in by Ralf Corsepius <ralf.corsepius@…>, on Dec 4, 2009 at 5:25:30 AM

Whitespace removal.

  • Property mode set to 100644
File size: 5.0 KB
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1/*
2 *  This file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 *           Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 *  This program is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 *  COPYRIGHT (c) 1998-2001.
16 *  On-Line Applications Research Corporation (OAR).
17 *
18 *  The license and distribution terms for this file may be
19 *  found in the file LICENSE in this distribution or at
20 *  http://www.rtems.com/license/LICENSE.
21 *
22 *  $Id$
23 */
24
25#include <rtems/system.h>
26#include <rtems/score/isr.h>
27#include <rtems/score/sh_io.h>
28#include <rtems/score/cpu.h>
29#include <rtems/score/sh.h>
30
31/* referenced in start.S */
32extern proc_ptr vectab[] ;
33
34proc_ptr vectab[256] ;
35
36extern proc_ptr _Hardware_isr_Table[];
37
38/*  _CPU_Initialize
39 *
40 *  This routine performs processor dependent initialization.
41 *
42 *  INPUT PARAMETERS: NONE
43 */
44
45void _CPU_Initialize(void)
46{
47  register uint32_t   level = 0;
48
49  /*
50   *  If there is not an easy way to initialize the FP context
51   *  during Context_Initialize, then it is usually easier to
52   *  save an "uninitialized" FP context here and copy it to
53   *  the task's during Context_Initialize.
54   */
55
56  /* FP context initialization support goes here */
57  /* FIXME: When not to use SH4_FPSCR_PR ? */
58#ifdef __SH4__
59  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR;
60#endif
61#ifdef __SH3E__
62  /* FIXME: Wild guess :) */
63  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM;
64#endif
65
66  /* enable interrupts */
67  _CPU_ISR_Set_level( level ) ;
68}
69
70/*PAGE
71 *
72 *  _CPU_ISR_Get_level
73 */
74
75uint32_t   _CPU_ISR_Get_level( void )
76{
77  /*
78   *  This routine returns the current interrupt level.
79   */
80
81  register uint32_t   _mask ;
82
83  sh_get_interrupt_level( _mask );
84
85  return ( _mask);
86}
87
88/*PAGE
89 *
90 *  _CPU_ISR_install_raw_handler
91 */
92
93void _CPU_ISR_install_raw_handler(
94  uint32_t    vector,
95  proc_ptr    new_handler,
96  proc_ptr   *old_handler
97)
98{
99  /*
100   *  This is where we install the interrupt handler into the "raw" interrupt
101   *  table used by the CPU to dispatch interrupt handlers.
102   */
103  volatile proc_ptr     *vbr ;
104
105#if SH_PARANOID_ISR
106  uint32_t              level ;
107
108  sh_disable_interrupts( level );
109#endif
110
111  /* get vbr */
112  asm ( "stc vbr,%0" : "=r" (vbr) );
113
114  *old_handler = vbr[vector] ;
115  vbr[vector]  = new_handler ;
116
117#if SH_PARANOID_ISR
118  sh_enable_interrupts( level );
119#endif
120}
121
122
123/*PAGE
124 *
125 *  _CPU_ISR_install_vector
126 *
127 *  This kernel routine installs the RTEMS handler for the
128 *  specified vector.
129 *
130 *  Input parameters:
131 *    vector      - interrupt vector number
132 *    old_handler - former ISR for this vector number
133 *    new_handler - replacement ISR for this vector number
134 *
135 *  Output parameters:  NONE
136 *
137 */
138
139void _CPU_ISR_install_vector(
140  uint32_t    vector,
141  proc_ptr    new_handler,
142  proc_ptr   *old_handler
143)
144{
145   proc_ptr ignored ;
146   *old_handler = _ISR_Vector_table[ vector ];
147
148 /*
149  *  If the interrupt vector table is a table of pointer to isr entry
150  *  points, then we need to install the appropriate RTEMS interrupt
151  *  handler for this vector number.
152  */
153#if defined(__sh1__) || defined(__sh2__)
154  _CPU_ISR_install_raw_handler(vector, _Hardware_isr_Table[vector], &ignored );
155#endif
156
157 /*
158  *  We put the actual user ISR address in '_ISR_Vector_table'.
159  *  This will be used by __ISR_Handler so the user gets control.
160  */
161
162 _ISR_Vector_table[ vector ] = new_handler;
163}
164
165/*PAGE
166 *
167 *  _CPU_Thread_Idle_body
168 *
169 *  NOTES:
170 *
171 *  1. This is the same as the regular CPU independent algorithm.
172 *
173 *  2. If you implement this using a "halt", "idle", or "shutdown"
174 *     instruction, then don't forget to put it in an infinite loop.
175 *
176 *  3. Be warned. Some processors with onboard DMA have been known
177 *     to stop the DMA if the CPU were put in IDLE mode.  This might
178 *     also be a problem with other on-chip peripherals.  So use this
179 *     hook with caution.
180 */
181
182#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
183void *_CPU_Thread_Idle_body( uintptr_t ignored )
184{
185
186  for( ; ; )
187    {
188      asm volatile("nop");
189    }
190    /* insert your "halt" instruction here */ ;
191}
192#endif
193
194#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
195
196uint8_t   _bit_set_table[16] =
197  { 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0};
198
199
200#endif
201
202void _CPU_Context_Initialize(
203  Context_Control       *_the_context,
204  void                  *_stack_base,
205  uint32_t              _size,
206  uint32_t              _isr,
207  void  (*_entry_point)(void),
208  int                   _is_fp )
209{
210  _the_context->r15 = (uint32_t *) ((uint32_t) (_stack_base) + (_size) );
211#if defined(__sh1__) || defined(__sh2__) || defined(__SH2E__)
212  _the_context->sr  = (_isr << 4) & 0x00f0 ;
213#else
214  _the_context->sr  = SH4_SR_MD | ((_isr << 4) & 0x00f0);
215#endif
216  _the_context->pr  = (uint32_t *) _entry_point ;
217
218
219#if 0 && SH_HAS_FPU
220   /* Disable FPU if it is non-fp task */
221  if(!_is_fp)
222    _the_context->sr |= SH4_SR_FD;
223#endif
224}
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