1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief SuperH CPU Support |
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5 | * |
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6 | * This file contains information pertaining to the Hitachi SH |
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7 | * processor. |
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8 | */ |
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9 | |
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10 | /* |
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11 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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12 | * Bernd Becker (becker@faw.uni-ulm.de) |
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13 | * |
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14 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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15 | * |
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16 | * This program is distributed in the hope that it will be useful, |
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17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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19 | * |
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20 | * |
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21 | * COPYRIGHT (c) 1998-2001. |
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22 | * On-Line Applications Research Corporation (OAR). |
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23 | * |
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24 | * The license and distribution terms for this file may be |
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25 | * found in the file LICENSE in this distribution or at |
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26 | * http://www.rtems.org/license/LICENSE. |
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27 | */ |
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28 | |
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29 | #ifdef HAVE_CONFIG_H |
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30 | #include "config.h" |
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31 | #endif |
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32 | |
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33 | #include <rtems/system.h> |
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34 | #include <rtems/score/isr.h> |
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35 | #include <rtems/score/sh_io.h> |
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36 | #include <rtems/score/cpu.h> |
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37 | #include <rtems/score/sh.h> |
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38 | |
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39 | /* referenced in start.S */ |
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40 | CPU_ISR_raw_handler vectab[256] ; |
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41 | |
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42 | #if SH_HAS_FPU |
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43 | Context_Control_fp _CPU_Null_fp_context; |
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44 | #endif |
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45 | |
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46 | /* _CPU_Initialize |
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47 | * |
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48 | * This routine performs processor dependent initialization. |
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49 | * |
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50 | * INPUT PARAMETERS: NONE |
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51 | */ |
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52 | |
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53 | void _CPU_Initialize(void) |
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54 | { |
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55 | register uint32_t level = 0; |
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56 | |
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57 | /* |
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58 | * If there is not an easy way to initialize the FP context |
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59 | * during Context_Initialize, then it is usually easier to |
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60 | * save an "uninitialized" FP context here and copy it to |
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61 | * the task's during Context_Initialize. |
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62 | */ |
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63 | |
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64 | /* FP context initialization support goes here */ |
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65 | #if SH_HAS_FPU |
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66 | /* FIXME: When not to use SH4_FPSCR_PR ? */ |
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67 | #ifdef __SH4__ |
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68 | _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR; |
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69 | #endif |
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70 | #ifdef __SH3E__ |
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71 | /* FIXME: Wild guess :) */ |
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72 | _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM; |
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73 | #endif |
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74 | #endif |
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75 | |
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76 | /* enable interrupts */ |
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77 | _CPU_ISR_Set_level( level ) ; |
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78 | } |
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79 | |
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80 | /* |
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81 | * _CPU_ISR_Get_level |
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82 | */ |
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83 | |
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84 | uint32_t _CPU_ISR_Get_level( void ) |
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85 | { |
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86 | /* |
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87 | * This routine returns the current interrupt level. |
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88 | */ |
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89 | |
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90 | register uint32_t _mask ; |
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91 | |
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92 | sh_get_interrupt_level( _mask ); |
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93 | |
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94 | return ( _mask); |
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95 | } |
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96 | |
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97 | void _CPU_ISR_install_raw_handler( |
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98 | uint32_t vector, |
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99 | CPU_ISR_raw_handler new_handler, |
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100 | CPU_ISR_raw_handler *old_handler |
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101 | ) |
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102 | |
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103 | { |
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104 | /* |
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105 | * This is where we install the interrupt handler into the "raw" interrupt |
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106 | * table used by the CPU to dispatch interrupt handlers. |
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107 | */ |
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108 | volatile CPU_ISR_raw_handler *vbr ; |
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109 | |
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110 | #if SH_PARANOID_ISR |
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111 | uint32_t level ; |
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112 | |
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113 | sh_disable_interrupts( level ); |
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114 | #endif |
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115 | |
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116 | /* get vbr */ |
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117 | __asm__ ( "stc vbr,%0" : "=r" (vbr) ); |
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118 | |
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119 | *old_handler = vbr[vector] ; |
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120 | vbr[vector] = new_handler ; |
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121 | |
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122 | #if SH_PARANOID_ISR |
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123 | sh_enable_interrupts( level ); |
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124 | #endif |
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125 | } |
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126 | |
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127 | void _CPU_ISR_install_vector( |
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128 | uint32_t vector, |
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129 | CPU_ISR_handler new_handler, |
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130 | CPU_ISR_handler *old_handler |
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131 | ) |
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132 | { |
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133 | #if defined(__sh1__) || defined(__sh2__) |
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134 | CPU_ISR_raw_handler ignored ; |
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135 | #endif |
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136 | *old_handler = _ISR_Vector_table[ vector ]; |
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137 | |
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138 | /* |
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139 | * If the interrupt vector table is a table of pointer to isr entry |
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140 | * points, then we need to install the appropriate RTEMS interrupt |
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141 | * handler for this vector number. |
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142 | */ |
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143 | #if defined(__sh1__) || defined(__sh2__) |
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144 | _CPU_ISR_install_raw_handler(vector, _Hardware_isr_Table[vector], &ignored ); |
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145 | #endif |
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146 | |
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147 | /* |
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148 | * We put the actual user ISR address in '_ISR_Vector_table'. |
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149 | * This will be used by __ISR_Handler so the user gets control. |
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150 | */ |
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151 | |
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152 | _ISR_Vector_table[ vector ] = new_handler; |
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153 | } |
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154 | |
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155 | void _CPU_Context_Initialize( |
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156 | Context_Control *_the_context, |
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157 | void *_stack_base, |
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158 | uint32_t _size, |
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159 | uint32_t _isr, |
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160 | void (*_entry_point)(void), |
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161 | int _is_fp, |
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162 | void *_tls_base) |
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163 | { |
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164 | _the_context->r15 = (uint32_t *) ((uint32_t) (_stack_base) + (_size) ); |
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165 | #if defined(__sh1__) || defined(__sh2__) || defined(__SH2E__) |
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166 | _the_context->sr = (_isr << 4) & 0x00f0 ; |
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167 | #else |
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168 | _the_context->sr = SH4_SR_MD | ((_isr << 4) & 0x00f0); |
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169 | #endif |
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170 | _the_context->pr = (uint32_t *) _entry_point ; |
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171 | |
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172 | |
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173 | #if 0 && SH_HAS_FPU |
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174 | /* Disable FPU if it is non-fp task */ |
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175 | if(!_is_fp) |
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176 | _the_context->sr |= SH4_SR_FD; |
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177 | #endif |
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178 | } |
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