source: rtems/cpukit/score/cpu/sh/cpu.c @ 4a238002

4.104.114.84.95
Last change on this file since 4a238002 was 4a238002, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 18, 1999 at 9:22:58 PM

Patch from "John M. Mills" <jmills@…> with subsequent cleanup from
Ralf Corsepius <corsepiu@…> that adds initial Hitachi SH-2
support to RTEMS. Ralf's comments are:

Changes:
------

  1. SH-Port:
  • Many files renamed.
  • CONSOLE_DEVNAME and MHZ defines removed from libcpu.
  • console.c moved to libbsp/sh/shared, build in libbsp/sh/<BSP>/console applying VPATH.
  • CONSOLE_DEVNAME made BSP-specific, replacement is defined in bsp.h
  • MHZ define replaced with HZ (extendent resolution) in custom/*.cfg
  • -DHZ=HZ used in bspstart.c, only
  • Makefile variable HZ used in bsp-dependent directories only.
  1. SH1-Port
  • clock-driver rewritten to provide better resolution for odd CPU frequencies. This driver is only partially tested on hardware, ie. sightly experimental, but I don't expect severe problems with it.
  • Polling SCI-driver added. This driver is experimental and completly untested yet. Therefore it is not yet used for the console (/dev/console is still pointing to /dev/null, cf. gensh1/bsp.h).
  • minor changes to the timer driver
  • SH1 specific delay()/CPU_delay() now is implemented as a function
  1. SH2-Port
  • Merged
  • IMO, the code is still in its infancy. Therefore I have interspersed comments (FIXME) it for items which I think John should look after.
  • sci and console drivers partially rewritten and extended (John, I hope you don't mind).
  • Copyright notices are not yet adapted
  • Property mode set to 100644
File size: 5.2 KB
Line 
1/*
2 *  This file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 *           Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 *  This program is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 *  COPYRIGHT (c) 1998.
16 *  On-Line Applications Research Corporation (OAR).
17 *  Copyright assigned to U.S. Government, 1994.
18 *
19 *  The license and distribution terms for this file may be
20 *  found in the file LICENSE in this distribution or at
21 *  http://www.OARcorp.com/rtems/license.html.
22 *
23 *  $Id$
24 */
25 
26#include <rtems/system.h>
27#include <rtems/score/isr.h>
28#include <rtems/score/sh_io.h>
29#include <rtems/score/cpu.h>
30#include <rtems/score/sh.h>
31
32
33/* referenced in start.S */
34extern proc_ptr vectab[] ;
35
36proc_ptr vectab[256] ;
37
38extern proc_ptr _Hardware_isr_Table[];
39
40/*  _CPU_Initialize
41 *
42 *  This routine performs processor dependent initialization.
43 *
44 *  INPUT PARAMETERS:
45 *    cpu_table       - CPU table to initialize
46 *    thread_dispatch - address of disptaching routine
47 */
48
49
50void _CPU_Initialize(
51  rtems_cpu_table  *cpu_table,
52  void      (*thread_dispatch)      /* ignored on this CPU */
53)
54{
55  register unsigned32 level = 0;
56
57  /*
58   *  The thread_dispatch argument is the address of the entry point
59   *  for the routine called at the end of an ISR once it has been
60   *  decided a context switch is necessary.  On some compilation
61   *  systems it is difficult to call a high-level language routine
62   *  from assembly.  This allows us to trick these systems.
63   *
64   *  If you encounter this problem save the entry point in a CPU
65   *  dependent variable.
66   */
67
68  _CPU_Thread_dispatch_pointer = thread_dispatch;
69
70  /*
71   *  If there is not an easy way to initialize the FP context
72   *  during Context_Initialize, then it is usually easier to
73   *  save an "uninitialized" FP context here and copy it to
74   *  the task's during Context_Initialize.
75   */
76
77  /* FP context initialization support goes here */
78
79  _CPU_Table = *cpu_table;
80
81  /* enable interrupts */
82  _CPU_ISR_Set_level( level);
83}
84
85/*PAGE
86 *
87 *  _CPU_ISR_Get_level
88 */
89 
90unsigned32 _CPU_ISR_Get_level( void )
91{
92  /*
93   *  This routine returns the current interrupt level.
94   */
95
96  register unsigned32 _mask ;
97 
98  sh_get_interrupt_level( _mask );
99 
100  return ( _mask);
101}
102
103/*PAGE
104 *
105 *  _CPU_ISR_install_raw_handler
106 */
107 
108void _CPU_ISR_install_raw_handler(
109  unsigned32  vector,
110  proc_ptr    new_handler,
111  proc_ptr   *old_handler
112)
113{
114  /*
115   *  This is where we install the interrupt handler into the "raw" interrupt
116   *  table used by the CPU to dispatch interrupt handlers.
117   */
118  volatile proc_ptr     *vbr ;
119
120#if SH_PARANOID_ISR 
121  unsigned32            level ;
122
123  sh_disable_interrupts( level );
124#endif   
125
126  /* get vbr */
127  asm ( "stc vbr,%0" : "=r" (vbr) );
128
129  *old_handler = vbr[vector] ;
130  vbr[vector]  = new_handler ;
131
132#if SH_PARANOID_ISR
133  sh_enable_interrupts( level );
134#endif
135}
136
137
138/*PAGE
139 *
140 *  _CPU_ISR_install_vector
141 *
142 *  This kernel routine installs the RTEMS handler for the
143 *  specified vector.
144 *
145 *  Input parameters:
146 *    vector      - interrupt vector number
147 *    old_handler - former ISR for this vector number
148 *    new_handler - replacement ISR for this vector number
149 *
150 *  Output parameters:  NONE
151 *
152 */
153
154void _CPU_ISR_install_vector(
155  unsigned32  vector,
156  proc_ptr    new_handler,
157  proc_ptr   *old_handler
158)
159{
160   proc_ptr ignored ;
161
162   if(( vector <= 113) && ( vector >= 11))
163     {
164       *old_handler = _ISR_Vector_table[ vector ];
165
166       /*
167        *  If the interrupt vector table is a table of pointer to isr entry
168        *  points, then we need to install the appropriate RTEMS interrupt
169        *  handler for this vector number.
170        */
171       _CPU_ISR_install_raw_handler(vector, 
172                                    _Hardware_isr_Table[vector],
173                                    &ignored );
174
175       /*
176        *  We put the actual user ISR address in '_ISR_Vector_table'. 
177        *  This will be used by __ISR_Handler so the user gets control.
178        */
179
180       _ISR_Vector_table[ vector ] = new_handler;
181     }
182}
183
184/*PAGE
185 *
186 *  _CPU_Thread_Idle_body
187 *
188 *  NOTES:
189 *
190 *  1. This is the same as the regular CPU independent algorithm.
191 *
192 *  2. If you implement this using a "halt", "idle", or "shutdown"
193 *     instruction, then don't forget to put it in an infinite loop.
194 *
195 *  3. Be warned. Some processors with onboard DMA have been known
196 *     to stop the DMA if the CPU were put in IDLE mode.  This might
197 *     also be a problem with other on-chip peripherals.  So use this
198 *     hook with caution.
199 */
200
201#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
202void _CPU_Thread_Idle_body( void )
203{
204
205  for( ; ; )
206    {
207      asm volatile("nop");
208    }
209    /* insert your "halt" instruction here */ ;
210}
211#endif
212
213#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
214
215unsigned8 _bit_set_table[16] = 
216  { 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0};
217
218
219#endif
220
221void _CPU_Context_Initialize(
222  Context_Control       *_the_context,
223  void                  *_stack_base,
224  unsigned32            _size,
225  unsigned32            _isr,
226  void  (*_entry_point)(void),
227  int                   _is_fp )
228{
229  _the_context->r15 = (unsigned32*) ((unsigned32) (_stack_base) + (_size) );
230  _the_context->sr  = (_isr << 4) & 0x00f0 ;
231  _the_context->pr  = (unsigned32*) _entry_point ;
232}
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