source: rtems/cpukit/score/cpu/sh/cpu.c @ 022851a

4.115
Last change on this file since 022851a was 022851a, checked in by Sebastian Huber <sebastian.huber@…>, on 01/28/14 at 11:10:08

Add thread-local storage (TLS) support

Tested and implemented on ARM, m68k, PowerPC and SPARC. Other
architectures need more work.

  • Property mode set to 100644
File size: 5.1 KB
Line 
1/**
2 * @file
3 *
4 * @brief SuperH CPU Support
5 *
6 * This file contains information pertaining to the Hitachi SH
7 * processor.
8 */
9
10/*
11 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
12 *           Bernd Becker (becker@faw.uni-ulm.de)
13 *
14 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
15 *
16 *  This program is distributed in the hope that it will be useful,
17 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 *
20 *
21 *  COPYRIGHT (c) 1998-2001.
22 *  On-Line Applications Research Corporation (OAR).
23 *
24 *  The license and distribution terms for this file may be
25 *  found in the file LICENSE in this distribution or at
26 *  http://www.rtems.com/license/LICENSE.
27 */
28
29#ifdef HAVE_CONFIG_H
30#include "config.h"
31#endif
32
33#include <rtems/system.h>
34#include <rtems/score/isr.h>
35#include <rtems/score/sh_io.h>
36#include <rtems/score/cpu.h>
37#include <rtems/score/sh.h>
38
39/* referenced in start.S */
40extern proc_ptr vectab[] ;
41
42proc_ptr vectab[256] ;
43
44extern proc_ptr _Hardware_isr_Table[];
45
46/*  _CPU_Initialize
47 *
48 *  This routine performs processor dependent initialization.
49 *
50 *  INPUT PARAMETERS: NONE
51 */
52
53void _CPU_Initialize(void)
54{
55  register uint32_t   level = 0;
56
57  /*
58   *  If there is not an easy way to initialize the FP context
59   *  during Context_Initialize, then it is usually easier to
60   *  save an "uninitialized" FP context here and copy it to
61   *  the task's during Context_Initialize.
62   */
63
64  /* FP context initialization support goes here */
65  /* FIXME: When not to use SH4_FPSCR_PR ? */
66#ifdef __SH4__
67  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR;
68#endif
69#ifdef __SH3E__
70  /* FIXME: Wild guess :) */
71  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM;
72#endif
73
74  /* enable interrupts */
75  _CPU_ISR_Set_level( level ) ;
76}
77
78/*
79 *  _CPU_ISR_Get_level
80 */
81
82uint32_t   _CPU_ISR_Get_level( void )
83{
84  /*
85   *  This routine returns the current interrupt level.
86   */
87
88  register uint32_t   _mask ;
89
90  sh_get_interrupt_level( _mask );
91
92  return ( _mask);
93}
94
95/*
96 *  _CPU_ISR_install_raw_handler
97 */
98
99void _CPU_ISR_install_raw_handler(
100  uint32_t    vector,
101  proc_ptr    new_handler,
102  proc_ptr   *old_handler
103)
104{
105  /*
106   *  This is where we install the interrupt handler into the "raw" interrupt
107   *  table used by the CPU to dispatch interrupt handlers.
108   */
109  volatile proc_ptr     *vbr ;
110
111#if SH_PARANOID_ISR
112  uint32_t              level ;
113
114  sh_disable_interrupts( level );
115#endif
116
117  /* get vbr */
118  __asm__ ( "stc vbr,%0" : "=r" (vbr) );
119
120  *old_handler = vbr[vector] ;
121  vbr[vector]  = new_handler ;
122
123#if SH_PARANOID_ISR
124  sh_enable_interrupts( level );
125#endif
126}
127
128
129/*
130 *  _CPU_ISR_install_vector
131 *
132 *  This kernel routine installs the RTEMS handler for the
133 *  specified vector.
134 *
135 *  Input parameters:
136 *    vector      - interrupt vector number
137 *    old_handler - former ISR for this vector number
138 *    new_handler - replacement ISR for this vector number
139 *
140 *  Output parameters:  NONE
141 *
142 */
143
144void _CPU_ISR_install_vector(
145  uint32_t    vector,
146  proc_ptr    new_handler,
147  proc_ptr   *old_handler
148)
149{
150#if defined(__sh1__) || defined(__sh2__)
151   proc_ptr ignored ;
152#endif
153   *old_handler = _ISR_Vector_table[ vector ];
154
155 /*
156  *  If the interrupt vector table is a table of pointer to isr entry
157  *  points, then we need to install the appropriate RTEMS interrupt
158  *  handler for this vector number.
159  */
160#if defined(__sh1__) || defined(__sh2__)
161  _CPU_ISR_install_raw_handler(vector, _Hardware_isr_Table[vector], &ignored );
162#endif
163
164 /*
165  *  We put the actual user ISR address in '_ISR_Vector_table'.
166  *  This will be used by __ISR_Handler so the user gets control.
167  */
168
169 _ISR_Vector_table[ vector ] = new_handler;
170}
171
172/*
173 *  _CPU_Thread_Idle_body
174 *
175 *  NOTES:
176 *
177 *  1. This is the same as the regular CPU independent algorithm.
178 *
179 *  2. If you implement this using a "halt", "idle", or "shutdown"
180 *     instruction, then don't forget to put it in an infinite loop.
181 *
182 *  3. Be warned. Some processors with onboard DMA have been known
183 *     to stop the DMA if the CPU were put in IDLE mode.  This might
184 *     also be a problem with other on-chip peripherals.  So use this
185 *     hook with caution.
186 */
187
188#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
189void *_CPU_Thread_Idle_body( uintptr_t ignored )
190{
191
192  for( ; ; )
193    {
194      __asm__ volatile("nop");
195    }
196    /* insert your "halt" instruction here */ ;
197}
198#endif
199
200#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
201
202uint8_t   _bit_set_table[16] =
203  { 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0};
204
205
206#endif
207
208void _CPU_Context_Initialize(
209  Context_Control       *_the_context,
210  void                  *_stack_base,
211  uint32_t              _size,
212  uint32_t              _isr,
213  void  (*_entry_point)(void),
214  int                   _is_fp,
215  void                  *_tls_base)
216{
217  _the_context->r15 = (uint32_t *) ((uint32_t) (_stack_base) + (_size) );
218#if defined(__sh1__) || defined(__sh2__) || defined(__SH2E__)
219  _the_context->sr  = (_isr << 4) & 0x00f0 ;
220#else
221  _the_context->sr  = SH4_SR_MD | ((_isr << 4) & 0x00f0);
222#endif
223  _the_context->pr  = (uint32_t *) _entry_point ;
224
225
226#if 0 && SH_HAS_FPU
227   /* Disable FPU if it is non-fp task */
228  if(!_is_fp)
229    _the_context->sr |= SH4_SR_FD;
230#endif
231}
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