[50cf94da] | 1 | /* |
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| 2 | * This file contains information pertaining to the Hitachi SH |
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| 3 | * processor. |
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| 4 | * |
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| 5 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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| 6 | * Bernd Becker (becker@faw.uni-ulm.de) |
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| 7 | * |
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| 8 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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| 9 | * |
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| 10 | * This program is distributed in the hope that it will be useful, |
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| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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| 13 | * |
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| 14 | * |
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[7d953c2] | 15 | * COPYRIGHT (c) 1998-2001. |
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[50cf94da] | 16 | * On-Line Applications Research Corporation (OAR). |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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[7f28803d] | 20 | * http://www.rtems.com/license/LICENSE. |
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[50cf94da] | 21 | * |
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| 22 | * $Id$ |
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| 23 | */ |
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| 24 | |
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| 25 | #include <rtems/system.h> |
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| 26 | #include <rtems/score/isr.h> |
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| 27 | #include <rtems/score/sh_io.h> |
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| 28 | #include <rtems/score/cpu.h> |
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| 29 | #include <rtems/score/sh.h> |
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| 30 | |
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[4a238002] | 31 | /* referenced in start.S */ |
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[50cf94da] | 32 | extern proc_ptr vectab[] ; |
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| 33 | |
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| 34 | proc_ptr vectab[256] ; |
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| 35 | |
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| 36 | extern proc_ptr _Hardware_isr_Table[]; |
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| 37 | |
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| 38 | /* _CPU_Initialize |
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| 39 | * |
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| 40 | * This routine performs processor dependent initialization. |
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| 41 | * |
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| 42 | * INPUT PARAMETERS: |
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| 43 | * cpu_table - CPU table to initialize |
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| 44 | * thread_dispatch - address of disptaching routine |
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| 45 | */ |
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| 46 | |
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| 47 | |
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| 48 | void _CPU_Initialize( |
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| 49 | rtems_cpu_table *cpu_table, |
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| 50 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 51 | ) |
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| 52 | { |
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| 53 | register unsigned32 level = 0; |
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| 54 | |
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| 55 | /* |
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| 56 | * The thread_dispatch argument is the address of the entry point |
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| 57 | * for the routine called at the end of an ISR once it has been |
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| 58 | * decided a context switch is necessary. On some compilation |
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| 59 | * systems it is difficult to call a high-level language routine |
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| 60 | * from assembly. This allows us to trick these systems. |
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| 61 | * |
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| 62 | * If you encounter this problem save the entry point in a CPU |
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| 63 | * dependent variable. |
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| 64 | */ |
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| 65 | |
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| 66 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
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| 67 | |
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| 68 | /* |
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| 69 | * If there is not an easy way to initialize the FP context |
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| 70 | * during Context_Initialize, then it is usually easier to |
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| 71 | * save an "uninitialized" FP context here and copy it to |
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| 72 | * the task's during Context_Initialize. |
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| 73 | */ |
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| 74 | |
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| 75 | /* FP context initialization support goes here */ |
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[bc5fc7a6] | 76 | /* FIXME: When not to use SH4_FPSCR_PR ? */ |
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| 77 | #ifdef __SH4__ |
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| 78 | _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR; |
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| 79 | #endif |
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| 80 | #ifdef __SH3E__ |
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| 81 | /* FIXME: Wild guess :) */ |
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| 82 | _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM; |
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| 83 | #endif |
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[50cf94da] | 84 | |
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| 85 | _CPU_Table = *cpu_table; |
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| 86 | |
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| 87 | /* enable interrupts */ |
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| 88 | _CPU_ISR_Set_level( level); |
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| 89 | } |
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| 90 | |
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| 91 | /*PAGE |
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| 92 | * |
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| 93 | * _CPU_ISR_Get_level |
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| 94 | */ |
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| 95 | |
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| 96 | unsigned32 _CPU_ISR_Get_level( void ) |
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| 97 | { |
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| 98 | /* |
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| 99 | * This routine returns the current interrupt level. |
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| 100 | */ |
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| 101 | |
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| 102 | register unsigned32 _mask ; |
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| 103 | |
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| 104 | sh_get_interrupt_level( _mask ); |
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| 105 | |
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| 106 | return ( _mask); |
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| 107 | } |
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| 108 | |
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| 109 | /*PAGE |
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| 110 | * |
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| 111 | * _CPU_ISR_install_raw_handler |
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| 112 | */ |
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| 113 | |
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| 114 | void _CPU_ISR_install_raw_handler( |
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| 115 | unsigned32 vector, |
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| 116 | proc_ptr new_handler, |
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| 117 | proc_ptr *old_handler |
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| 118 | ) |
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| 119 | { |
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| 120 | /* |
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| 121 | * This is where we install the interrupt handler into the "raw" interrupt |
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| 122 | * table used by the CPU to dispatch interrupt handlers. |
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| 123 | */ |
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| 124 | volatile proc_ptr *vbr ; |
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| 125 | |
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| 126 | #if SH_PARANOID_ISR |
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| 127 | unsigned32 level ; |
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| 128 | |
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| 129 | sh_disable_interrupts( level ); |
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| 130 | #endif |
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| 131 | |
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| 132 | /* get vbr */ |
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| 133 | asm ( "stc vbr,%0" : "=r" (vbr) ); |
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| 134 | |
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| 135 | *old_handler = vbr[vector] ; |
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| 136 | vbr[vector] = new_handler ; |
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| 137 | |
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| 138 | #if SH_PARANOID_ISR |
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| 139 | sh_enable_interrupts( level ); |
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| 140 | #endif |
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| 141 | } |
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| 142 | |
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| 143 | |
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| 144 | /*PAGE |
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| 145 | * |
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| 146 | * _CPU_ISR_install_vector |
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| 147 | * |
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| 148 | * This kernel routine installs the RTEMS handler for the |
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| 149 | * specified vector. |
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| 150 | * |
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| 151 | * Input parameters: |
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| 152 | * vector - interrupt vector number |
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| 153 | * old_handler - former ISR for this vector number |
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| 154 | * new_handler - replacement ISR for this vector number |
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| 155 | * |
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| 156 | * Output parameters: NONE |
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| 157 | * |
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| 158 | */ |
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| 159 | |
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[3bcc0d8] | 160 | #if defined(__sh1__) || defined(__sh2__) |
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[50cf94da] | 161 | void _CPU_ISR_install_vector( |
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| 162 | unsigned32 vector, |
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| 163 | proc_ptr new_handler, |
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| 164 | proc_ptr *old_handler |
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| 165 | ) |
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| 166 | { |
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| 167 | proc_ptr ignored ; |
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[f30a0ca9] | 168 | #if 0 |
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[50cf94da] | 169 | if(( vector <= 113) && ( vector >= 11)) |
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| 170 | { |
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[f30a0ca9] | 171 | #endif |
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[50cf94da] | 172 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 173 | |
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| 174 | /* |
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| 175 | * If the interrupt vector table is a table of pointer to isr entry |
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| 176 | * points, then we need to install the appropriate RTEMS interrupt |
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| 177 | * handler for this vector number. |
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| 178 | */ |
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| 179 | _CPU_ISR_install_raw_handler(vector, |
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| 180 | _Hardware_isr_Table[vector], |
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| 181 | &ignored ); |
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| 182 | |
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| 183 | /* |
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| 184 | * We put the actual user ISR address in '_ISR_Vector_table'. |
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| 185 | * This will be used by __ISR_Handler so the user gets control. |
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| 186 | */ |
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| 187 | |
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| 188 | _ISR_Vector_table[ vector ] = new_handler; |
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[f30a0ca9] | 189 | #if 0 |
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[50cf94da] | 190 | } |
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[f30a0ca9] | 191 | #endif |
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[50cf94da] | 192 | } |
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[3bcc0d8] | 193 | #endif /* _CPU_ISR_install_vector */ |
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[50cf94da] | 194 | |
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| 195 | /*PAGE |
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| 196 | * |
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| 197 | * _CPU_Thread_Idle_body |
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| 198 | * |
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| 199 | * NOTES: |
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| 200 | * |
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| 201 | * 1. This is the same as the regular CPU independent algorithm. |
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| 202 | * |
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| 203 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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| 204 | * instruction, then don't forget to put it in an infinite loop. |
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| 205 | * |
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| 206 | * 3. Be warned. Some processors with onboard DMA have been known |
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| 207 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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| 208 | * also be a problem with other on-chip peripherals. So use this |
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| 209 | * hook with caution. |
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| 210 | */ |
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| 211 | |
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| 212 | #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) |
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| 213 | void _CPU_Thread_Idle_body( void ) |
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| 214 | { |
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| 215 | |
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| 216 | for( ; ; ) |
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| 217 | { |
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| 218 | asm volatile("nop"); |
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| 219 | } |
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| 220 | /* insert your "halt" instruction here */ ; |
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| 221 | } |
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| 222 | #endif |
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| 223 | |
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| 224 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
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| 225 | |
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| 226 | unsigned8 _bit_set_table[16] = |
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| 227 | { 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0}; |
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| 228 | |
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| 229 | |
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| 230 | #endif |
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| 231 | |
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| 232 | void _CPU_Context_Initialize( |
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| 233 | Context_Control *_the_context, |
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| 234 | void *_stack_base, |
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| 235 | unsigned32 _size, |
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| 236 | unsigned32 _isr, |
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| 237 | void (*_entry_point)(void), |
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| 238 | int _is_fp ) |
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| 239 | { |
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| 240 | _the_context->r15 = (unsigned32*) ((unsigned32) (_stack_base) + (_size) ); |
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[bc5fc7a6] | 241 | #if defined(__sh1__) || defined(__sh2__) |
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[50cf94da] | 242 | _the_context->sr = (_isr << 4) & 0x00f0 ; |
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[bc5fc7a6] | 243 | #else |
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| 244 | _the_context->sr = SH4_SR_MD | ((_isr << 4) & 0x00f0); |
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| 245 | #endif |
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[50cf94da] | 246 | _the_context->pr = (unsigned32*) _entry_point ; |
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[bc5fc7a6] | 247 | |
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| 248 | |
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| 249 | #if 0 && SH_HAS_FPU |
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| 250 | /* Disable FPU if it is non-fp task */ |
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| 251 | if(!_is_fp) |
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| 252 | _the_context->sr |= SH4_SR_FD; |
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| 253 | #endif |
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[50cf94da] | 254 | } |
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[bc5fc7a6] | 255 | |
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