source: rtems/cpukit/score/cpu/riscv32/riscv-context-initialize.c @ 660db8c8

Last change on this file since 660db8c8 was 660db8c8, checked in by Hesham Almatary <hesham@…>, on Oct 26, 2017 at 11:12:41 PM

cpukit: Add basic riscv32 architecture port v3

Limitations:

  • NO FPU support [TODO]

Update #3109

  • Property mode set to 100644
File size: 2.3 KB
Line 
1/*
2 *
3 * Copyright (c) 2015 University of York.
4 * Hesham Almatary <hesham@alumni.york.ac.uk>
5 *
6 * COPYRIGHT (c) 1989-2006.
7 * On-Line Applications Research Corporation (OAR).
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#ifdef HAVE_CONFIG_H
32#include "config.h"
33#endif
34
35#include <string.h>
36
37#include <rtems/score/cpu.h>
38#include <rtems/score/riscv-utility.h>
39#include <rtems/score/interr.h>
40
41void _CPU_Context_Initialize(
42  Context_Control *context,
43  void *stack_area_begin,
44  size_t stack_area_size,
45  uint32_t new_level,
46  void (*entry_point)( void ),
47  bool is_fp,
48  void *tls_area
49)
50{
51  uintptr_t stack = ((uintptr_t) stack_area_begin);
52
53  /* Account for red-zone */
54  uintptr_t stack_high = stack + stack_area_size - RISCV_GCC_RED_ZONE_SIZE;
55
56  memset(context, 0, sizeof(*context));
57
58  /* Stack Pointer - sp/x2 */
59  context->x[2] = stack_high;
60  /* Frame Pointer - fp/x8 */
61  context->x[8] = stack_high;
62  /* Return Address - ra/x1 */
63  context->x[1] = (uintptr_t) entry_point;
64
65  /* Enable interrupts and FP */
66  context->mstatus = MSTATUS_FS | MSTATUS_MIE;
67}
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