source: rtems/cpukit/score/cpu/riscv/rtems/score/types.h @ 11ff3a9

5
Last change on this file since 11ff3a9 was 11ff3a9, checked in by Hesham Almatary <heshamelmatary@…>, on 10/27/17 at 04:18:40

cpukit: RISC-V - make riscv32 code work for riscv64 - v2

  • Use #ifdefs for 32/64 bit code
  • Use unsigned long which is 32-bit on riscv32 and 64-bit on riscv64 (register size)
  • Move the code to a new shared riscv folder to be shared between riscv32 and riscv64
  • Rename RTEMS_CPU extracted from command line to shared riscv target s/riscv*/riscv

Update #3109
  • Property mode set to 100644
File size: 2.0 KB
Line 
1/**
2 * @file
3 *
4 * @brief RISC-V Architecture Types API
5 */
6
7/*
8 *  This include file contains type definitions pertaining to the
9 *  RISC-V processor family.
10 *
11 *  COPYRIGHT (c) 2014 Hesham Almatary <heshamelmatary@gmail.com>
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35#ifndef _RTEMS_SCORE_TYPES_H
36#define _RTEMS_SCORE_TYPES_H
37
38#include <rtems/score/basedefs.h>
39
40#ifndef ASM
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
46/**
47 * @addtogroup ScoreCPU
48 */
49/**@{**/
50
51/*
52 *  This section defines the basic types for this processor.
53 */
54
55/** Type that can store a 32-bit integer or a pointer. */
56typedef uintptr_t CPU_Uint32ptr;
57
58typedef uint16_t Priority_bit_map_Word;
59typedef void riscv_isr;
60typedef void ( *riscv_isr_entry )( void );
61
62/** @} */
63
64#ifdef __cplusplus
65}
66#endif
67
68#endif  /* !ASM */
69
70#endif
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