source: rtems/cpukit/score/cpu/riscv/rtems/score/cpu_asm.h @ 11ff3a9

5
Last change on this file since 11ff3a9 was 11ff3a9, checked in by Hesham Almatary <heshamelmatary@…>, on 10/27/17 at 04:18:40

cpukit: RISC-V - make riscv32 code work for riscv64 - v2

  • Use #ifdefs for 32/64 bit code
  • Use unsigned long which is 32-bit on riscv32 and 64-bit on riscv64 (register size)
  • Move the code to a new shared riscv folder to be shared between riscv32 and riscv64
  • Rename RTEMS_CPU extracted from command line to shared riscv target s/riscv*/riscv

Update #3109
  • Property mode set to 100644
File size: 2.2 KB
Line 
1/**
2 * @file
3 *
4 * @brief riscv32 Assembly File
5 *
6 * Very loose template for an include file for the cpu_asm.? file
7 * if it is implemented as a ".S" file (preprocessed by cpp) instead
8 * of a ".s" file (preprocessed by gm4 or gasp).
9 */
10
11/*
12 *  COPYRIGHT (c) 1989-1999.
13 *  On-Line Applications Research Corporation (OAR).
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 *    notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 *    notice, this list of conditions and the following disclaimer in the
22 *    documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 */
36
37#ifndef _RTEMS_SCORE_CPU_ASM_H
38#define _RTEMS_SCORE_CPU_ASM_H
39
40/* pull in the generated offsets */
41
42/*
43#include <rtems/score/offsets.h>
44*/
45
46/*
47 * Hardware General Registers
48 */
49
50/* put something here */
51
52/*
53 * Hardware Floating Point Registers
54 */
55
56/* put something here */
57
58/*
59 * Hardware Control Registers
60 */
61
62/* put something here */
63
64/*
65 * Calling Convention
66 */
67
68/* put something here */
69
70/*
71 * Temporary registers
72 */
73
74/* put something here */
75
76/*
77 * Floating Point Registers - SW Conventions
78 */
79
80/* put something here */
81
82/*
83 * Temporary floating point registers
84 */
85
86/* put something here */
87
88#endif
89
90/* end of file */
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