source: rtems/cpukit/score/cpu/riscv/rtems/score/cpu.h @ 11ff3a9

Last change on this file since 11ff3a9 was 11ff3a9, checked in by Hesham Almatary <heshamelmatary@…>, on Oct 27, 2017 at 4:18:40 AM

cpukit: RISC-V - make riscv32 code work for riscv64 - v2

  • Use #ifdefs for 32/64 bit code
  • Use unsigned long which is 32-bit on riscv32 and 64-bit on riscv64 (register size)
  • Move the code to a new shared riscv folder to be shared between riscv32 and riscv64
  • Rename RTEMS_CPU extracted from command line to shared riscv target s/riscv*/riscv

Update #3109

  • Property mode set to 100644
File size: 15.5 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *
7 * Copyright (c) 2015 University of York.
8 * Hesham Almatary <hesham@alumni.york.ac.uk>
9 *
10 * COPYRIGHT (c) 1989-1999.
11 * On-Line Applications Research Corporation (OAR).
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35#ifndef _RISCV_CPU_H
36#define _RISCV_CPU_H
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42#include <rtems/score/riscv.h> /* pick up machine definitions */
43#include <rtems/score/types.h>
44#include <rtems/score/riscv-utility.h>
45#ifndef ASM
46#include <rtems/bspIo.h>
47#include <stdint.h>
48#include <stdio.h> /* for printk */
49#endif
50
51#define CPU_INLINE_ENABLE_DISPATCH       FALSE
52#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
53#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
54#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
55#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
56#define CPU_ISR_PASSES_FRAME_POINTER 1
57#define CPU_HARDWARE_FP                  FALSE
58#define CPU_SOFTWARE_FP                  FALSE
59#define CPU_ALL_TASKS_ARE_FP             FALSE
60#define CPU_IDLE_TASK_IS_FP              FALSE
61#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
62#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
63#define CPU_STACK_GROWS_UP               FALSE
64
65#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64)))
66#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
67#define CPU_BIG_ENDIAN                           FALSE
68#define CPU_LITTLE_ENDIAN                        TRUE
69#define CPU_MODES_INTERRUPT_MASK   0x0000000000000001
70
71/*
72 *  Processor defined structures required for cpukit/score.
73 */
74
75#ifndef ASM
76
77typedef struct {
78  /* riscv has 32 xlen-bit (where xlen can be 32 or 64) general purpose registers (x0-x31)*/
79  unsigned long x[32];
80
81  /* Special purpose registers */
82  unsigned long mstatus;
83  unsigned long mcause;
84  unsigned long mepc;
85#ifdef RTEMS_SMP
86  /**
87   * @brief On SMP configurations the thread context must contain a boolean
88   * indicator to signal if this context is executing on a processor.
89   *
90   * This field must be updated during a context switch.  The context switch
91   * to the heir must wait until the heir context indicates that it is no
92   * longer executing on a processor.  The context switch must also check if
93   * a thread dispatch is necessary to honor updates of the heir thread for
94   * this processor.  This indicator must be updated using an atomic test and
95   * set operation to ensure that at most one processor uses the heir
96   * context at the same time.
97   *
98   * @code
99   * void _CPU_Context_switch(
100   *   Context_Control *executing,
101   *   Context_Control *heir
102   * )
103   * {
104   *   save( executing );
105   *
106   *   executing->is_executing = false;
107   *   memory_barrier();
108   *
109   *   if ( test_and_set( &heir->is_executing ) ) {
110   *     do {
111   *       Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot();
112   *
113   *       if ( cpu_self->dispatch_necessary ) {
114   *         heir = _Thread_Get_heir_and_make_it_executing( cpu_self );
115   *       }
116   *     } while ( test_and_set( &heir->is_executing ) );
117   *   }
118   *
119   *   restore( heir );
120   * }
121   * @endcode
122   */
123  volatile bool is_executing;
124#endif
125} Context_Control;
126
127#define _CPU_Context_Get_SP( _context ) \
128  (_context)->x[2]
129
130typedef struct {
131  /** TODO FPU registers are listed here */
132  double  some_float_register;
133} Context_Control_fp;
134
135typedef Context_Control CPU_Interrupt_frame;
136
137#define CPU_CONTEXT_FP_SIZE  0
138Context_Control_fp  _CPU_Null_fp_context;
139
140#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
141#if __riscv_xlen == 32
142#define CPU_STACK_MINIMUM_SIZE  4096
143#else
144#define CPU_STACK_MINIMUM_SIZE  4096 * 2
145#endif
146#define CPU_ALIGNMENT 8
147#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
148#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
149#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
150#define CPU_STACK_ALIGNMENT        8
151#define _CPU_Initialize_vectors()
152
153/*
154 *  Disable all interrupts for an RTEMS critical section.  The previous
155 *  level is returned in _level.
156 *
157 */
158
159static inline unsigned long riscv_interrupt_disable( void )
160{
161  register unsigned long status = read_csr(mstatus);
162  clear_csr(mstatus, MSTATUS_MIE);
163  return status;
164}
165
166static inline void riscv_interrupt_enable(unsigned long level)
167{
168  write_csr(mstatus, level);
169}
170
171#define _CPU_ISR_Disable( _level ) \
172    _level = riscv_interrupt_disable()
173
174#define _CPU_ISR_Enable( _level )  \
175  riscv_interrupt_enable( _level )
176
177#define _CPU_ISR_Flash( _level ) \
178  do{ \
179      _CPU_ISR_Enable( _level ); \
180      riscv_interrupt_disable(); \
181    } while(0)
182
183RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level )
184{
185  return ( level & MSTATUS_MIE ) != 0;
186}
187
188void _CPU_ISR_Set_level( unsigned long level );
189
190unsigned long _CPU_ISR_Get_level( void );
191
192/* end of ISR handler macros */
193
194/* Context handler macros */
195#define RISCV_GCC_RED_ZONE_SIZE 128
196
197void _CPU_Context_Initialize(
198  Context_Control *context,
199  void *stack_area_begin,
200  size_t stack_area_size,
201  unsigned long new_level,
202  void (*entry_point)( void ),
203  bool is_fp,
204  void *tls_area
205);
206
207#define _CPU_Context_Restart_self( _the_context ) \
208   _CPU_Context_restore( (_the_context) )
209
210
211#define _CPU_Context_Fp_start( _base, _offset ) \
212   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
213
214#define _CPU_Context_Initialize_fp( _destination ) \
215  { \
216   *(*(_destination)) = _CPU_Null_fp_context; \
217  }
218
219extern void _CPU_Fatal_halt(uint32_t source, uint32_t error)
220RTEMS_NO_RETURN;
221
222/* end of Fatal Error manager macros */
223
224#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
225#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
226
227#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
228
229#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
230  { \
231    (_output) = 0;   /* do something to prevent warnings */ \
232  }
233#endif
234
235/* end of Bitfield handler macros */
236
237/*
238 *  This routine builds the mask which corresponds to the bit fields
239 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
240 *  for that routine.
241 *
242 */
243
244#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
245
246#define _CPU_Priority_Mask( _bit_number ) \
247    (1 << _bit_number)
248
249#endif
250
251#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
252
253#define _CPU_Priority_bits_index( _priority ) \
254  (_priority)
255
256#endif
257
258#define CPU_MAXIMUM_PROCESSORS 32
259
260#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE
261#define CPU_TIMESTAMP_USE_INT64 TRUE
262#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE
263
264typedef struct {
265  /* There is no CPU specific per-CPU state */
266} CPU_Per_CPU_control;
267#endif /* ASM */
268
269#if __riscv_xlen == 32
270#define CPU_SIZEOF_POINTER 4
271
272/* 32-bit load/store instructions */
273#define LREG lw
274#define SREG sw
275
276#define CPU_EXCEPTION_FRAME_SIZE 128
277#else /* xlen = 64 */
278#define CPU_SIZEOF_POINTER 8
279
280/* 64-bit load/store instructions */
281#define LREG ld
282#define SREG sd
283
284#define CPU_EXCEPTION_FRAME_SIZE 256
285#endif
286
287#define CPU_PER_CPU_CONTROL_SIZE 0
288
289#ifndef ASM
290typedef uint16_t Priority_bit_map_Word;
291
292typedef struct {
293  unsigned long x[32];;
294} CPU_Exception_frame;
295
296/**
297 * @brief Prints the exception frame via printk().
298 *
299 * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
300 */
301void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
302
303
304/* end of Priority handler macros */
305
306/* functions */
307
308/*
309 *  _CPU_Initialize
310 *
311 *  This routine performs CPU dependent initialization.
312 *
313 */
314
315void _CPU_Initialize(
316  void
317);
318
319/*
320 *  _CPU_ISR_install_raw_handler
321 *
322 *  This routine installs a "raw" interrupt handler directly into the
323 *  processor's vector table.
324 *
325 */
326
327void _CPU_ISR_install_raw_handler(
328  uint32_t    vector,
329  proc_ptr    new_handler,
330  proc_ptr   *old_handler
331);
332
333/*
334 *  _CPU_ISR_install_vector
335 *
336 *  This routine installs an interrupt vector.
337 *
338 *  NO_CPU Specific Information:
339 *
340 *  XXX document implementation including references if appropriate
341 */
342
343void _CPU_ISR_install_vector(
344  unsigned long    vector,
345  proc_ptr   new_handler,
346  proc_ptr   *old_handler
347);
348
349/*
350 *  _CPU_Install_interrupt_stack
351 *
352 *  This routine installs the hardware interrupt stack pointer.
353 *
354 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
355 *         is TRUE.
356 *
357 */
358
359void _CPU_Install_interrupt_stack( void );
360
361/*
362 *  _CPU_Thread_Idle_body
363 *
364 *  This routine is the CPU dependent IDLE thread body.
365 *
366 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
367 *         is TRUE.
368 *
369 */
370
371void *_CPU_Thread_Idle_body( uintptr_t ignored );
372
373/*
374 *  _CPU_Context_switch
375 *
376 *  This routine switches from the run context to the heir context.
377 *
378 *  RISCV Specific Information:
379 *
380 *  Please see the comments in the .c file for a description of how
381 *  this function works. There are several things to be aware of.
382 */
383
384void _CPU_Context_switch(
385  Context_Control  *run,
386  Context_Control  *heir
387);
388
389/*
390 *  _CPU_Context_restore
391 *
392 *  This routine is generally used only to restart self in an
393 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
394 *
395 *  NOTE: May be unnecessary to reload some registers.
396 *
397 */
398
399void _CPU_Context_restore(
400  Context_Control *new_context
401) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
402
403/*
404 *  _CPU_Context_save_fp
405 *
406 *  This routine saves the floating point context passed to it.
407 *
408 */
409
410void _CPU_Context_save_fp(
411  void **fp_context_ptr
412);
413
414/*
415 *  _CPU_Context_restore_fp
416 *
417 *  This routine restores the floating point context passed to it.
418 *
419 */
420
421void _CPU_Context_restore_fp(
422  void **fp_context_ptr
423);
424
425/*  The following routine swaps the endian format of an unsigned int.
426 *  It must be static because it is referenced indirectly.
427 *
428 *  This version will work on any processor, but if there is a better
429 *  way for your CPU PLEASE use it.  The most common way to do this is to:
430 *
431 *     swap least significant two bytes with 16-bit rotate
432 *     swap upper and lower 16-bits
433 *     swap most significant two bytes with 16-bit rotate
434 *
435 *  Some CPUs have special instructions which swap a 32-bit quantity in
436 *  a single instruction (e.g. i486).  It is probably best to avoid
437 *  an "endian swapping control bit" in the CPU.  One good reason is
438 *  that interrupts would probably have to be disabled to insure that
439 *  an interrupt does not try to access the same "chunk" with the wrong
440 *  endian.  Another good reason is that on some CPUs, the endian bit
441 *  endianness for ALL fetches -- both code and data -- so the code
442 *  will be fetched incorrectly.
443 *
444 */
445
446static inline uint32_t CPU_swap_u32(
447  uint32_t value
448)
449{
450  uint32_t   byte1, byte2, byte3, byte4, swapped;
451
452  byte4 = (value >> 24) & 0xff;
453  byte3 = (value >> 16) & 0xff;
454  byte2 = (value >> 8)  & 0xff;
455  byte1 =  value        & 0xff;
456
457  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
458  return ( swapped );
459}
460
461#define CPU_swap_u16( value ) \
462  (((value&0xff) << 8) | ((value >> 8)&0xff))
463
464static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
465{
466  /* TODO */
467}
468
469static inline void _CPU_Context_validate( uintptr_t pattern )
470{
471  while (1) {
472    /* TODO */
473  }
474}
475
476typedef uint32_t CPU_Counter_ticks;
477
478CPU_Counter_ticks _CPU_Counter_read( void );
479
480#ifdef RTEMS_SMP
481/**
482 * @brief Performs CPU specific SMP initialization in the context of the boot
483 * processor.
484 *
485 * This function is invoked on the boot processor during system
486 * initialization.  All interrupt stacks are allocated at this point in case
487 * the CPU port allocates the interrupt stacks.  This function is called
488 * before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is
489 * used.
490 *
491 * @return The count of physically or virtually available processors.
492 * Depending on the configuration the application may use not all processors.
493 */
494uint32_t _CPU_SMP_Initialize( void );
495
496/**
497 * @brief Starts a processor specified by its index.
498 *
499 * This function is invoked on the boot processor during system
500 * initialization.
501 *
502 * This function will be called after _CPU_SMP_Initialize().
503 *
504 * @param[in] cpu_index The processor index.
505 *
506 * @retval true Successful operation.
507 * @retval false Unable to start this processor.
508 */
509bool _CPU_SMP_Start_processor( uint32_t cpu_index );
510
511/**
512 * @brief Performs final steps of CPU specific SMP initialization in the
513 * context of the boot processor.
514 *
515 * This function is invoked on the boot processor during system
516 * initialization.
517 *
518 * This function will be called after all processors requested by the
519 * application have been started.
520 *
521 * @param[in] cpu_count The minimum value of the count of processors
522 * requested by the application configuration and the count of physically or
523 * virtually available processors.
524 */
525void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
526
527/**
528 * @brief Returns the index of the current processor.
529 *
530 * An architecture specific method must be used to obtain the index of the
531 * current processor in the system.  The set of processor indices is the
532 * range of integers starting with zero up to the processor count minus one.
533 */
534uint32_t _CPU_SMP_Get_current_processor( void );
535
536/**
537 * @brief Sends an inter-processor interrupt to the specified target
538 * processor.
539 *
540 * This operation is undefined for target processor indices out of range.
541 *
542 * @param[in] target_processor_index The target processor index.
543 */
544void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
545
546/**
547 * @brief Broadcasts a processor event.
548 *
549 * Some architectures provide a low-level synchronization primitive for
550 * processors in a multi-processor environment.  Processors waiting for this
551 * event may go into a low-power state and stop generating system bus
552 * transactions.  This function must ensure that preceding store operations
553 * can be observed by other processors.
554 *
555 * @see _CPU_SMP_Processor_event_receive().
556 */
557void _CPU_SMP_Processor_event_broadcast( void );
558
559/**
560 * @brief Receives a processor event.
561 *
562 * This function will wait for the processor event and may wait forever if no
563 * such event arrives.
564 *
565 * @see _CPU_SMP_Processor_event_broadcast().
566 */
567static inline void _CPU_SMP_Processor_event_receive( void )
568{
569  __asm__ volatile ( "" : : : "memory" );
570}
571
572/**
573 * @brief Gets the is executing indicator of the thread context.
574 *
575 * @param[in] context The context.
576 */
577static inline bool _CPU_Context_Get_is_executing(
578  const Context_Control *context
579)
580{
581  return context->is_executing;
582}
583
584/**
585 * @brief Sets the is executing indicator of the thread context.
586 *
587 * @param[in] context The context.
588 * @param[in] is_executing The new value for the is executing indicator.
589 */
590static inline void _CPU_Context_Set_is_executing(
591  Context_Control *context,
592  bool is_executing
593)
594{
595  context->is_executing = is_executing;
596}
597#endif /* RTEMS_SMP */
598
599#endif /* ASM */
600
601#ifdef __cplusplus
602}
603#endif
604
605#endif
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