[660db8c8] | 1 | /** |
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| 2 | * @file rtems/score/cpu.h |
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| 3 | */ |
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| 4 | |
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| 5 | /* |
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| 6 | * |
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| 7 | * Copyright (c) 2015 University of York. |
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| 8 | * Hesham Almatary <hesham@alumni.york.ac.uk> |
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| 9 | * |
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| 10 | * COPYRIGHT (c) 1989-1999. |
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| 11 | * On-Line Applications Research Corporation (OAR). |
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| 12 | * |
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| 13 | * Redistribution and use in source and binary forms, with or without |
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| 14 | * modification, are permitted provided that the following conditions |
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| 15 | * are met: |
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| 16 | * 1. Redistributions of source code must retain the above copyright |
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| 17 | * notice, this list of conditions and the following disclaimer. |
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| 18 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 19 | * notice, this list of conditions and the following disclaimer in the |
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| 20 | * documentation and/or other materials provided with the distribution. |
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| 21 | * |
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| 22 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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| 23 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 25 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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| 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 28 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 29 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 30 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 31 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 32 | * SUCH DAMAGE. |
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| 33 | */ |
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| 34 | |
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| 35 | #ifndef _RISCV_CPU_H |
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| 36 | #define _RISCV_CPU_H |
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| 37 | |
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| 38 | #ifdef __cplusplus |
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| 39 | extern "C" { |
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| 40 | #endif |
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| 41 | |
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| 42 | #include <rtems/score/riscv.h> /* pick up machine definitions */ |
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| 43 | #include <rtems/score/types.h> |
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| 44 | #include <rtems/score/riscv-utility.h> |
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| 45 | #ifndef ASM |
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| 46 | #include <rtems/bspIo.h> |
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| 47 | #include <stdint.h> |
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| 48 | #include <stdio.h> /* for printk */ |
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| 49 | #endif |
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| 50 | |
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| 51 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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| 52 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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| 53 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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| 54 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 55 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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| 56 | #define CPU_ISR_PASSES_FRAME_POINTER 1 |
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| 57 | #define CPU_HARDWARE_FP FALSE |
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| 58 | #define CPU_SOFTWARE_FP FALSE |
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| 59 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 60 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 61 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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| 62 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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| 63 | #define CPU_STACK_GROWS_UP FALSE |
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| 64 | |
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| 65 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64))) |
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| 66 | #define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE |
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| 67 | #define CPU_BIG_ENDIAN FALSE |
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| 68 | #define CPU_LITTLE_ENDIAN TRUE |
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[11ff3a9] | 69 | #define CPU_MODES_INTERRUPT_MASK 0x0000000000000001 |
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[660db8c8] | 70 | |
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| 71 | /* |
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| 72 | * Processor defined structures required for cpukit/score. |
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| 73 | */ |
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| 74 | |
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| 75 | #ifndef ASM |
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| 76 | |
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| 77 | typedef struct { |
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[11ff3a9] | 78 | /* riscv has 32 xlen-bit (where xlen can be 32 or 64) general purpose registers (x0-x31)*/ |
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| 79 | unsigned long x[32]; |
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[660db8c8] | 80 | |
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| 81 | /* Special purpose registers */ |
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[11ff3a9] | 82 | unsigned long mstatus; |
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| 83 | unsigned long mcause; |
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| 84 | unsigned long mepc; |
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[660db8c8] | 85 | #ifdef RTEMS_SMP |
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| 86 | /** |
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| 87 | * @brief On SMP configurations the thread context must contain a boolean |
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| 88 | * indicator to signal if this context is executing on a processor. |
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| 89 | * |
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| 90 | * This field must be updated during a context switch. The context switch |
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| 91 | * to the heir must wait until the heir context indicates that it is no |
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| 92 | * longer executing on a processor. The context switch must also check if |
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| 93 | * a thread dispatch is necessary to honor updates of the heir thread for |
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| 94 | * this processor. This indicator must be updated using an atomic test and |
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| 95 | * set operation to ensure that at most one processor uses the heir |
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| 96 | * context at the same time. |
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| 97 | * |
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| 98 | * @code |
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| 99 | * void _CPU_Context_switch( |
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| 100 | * Context_Control *executing, |
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| 101 | * Context_Control *heir |
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| 102 | * ) |
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| 103 | * { |
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| 104 | * save( executing ); |
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| 105 | * |
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| 106 | * executing->is_executing = false; |
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| 107 | * memory_barrier(); |
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| 108 | * |
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| 109 | * if ( test_and_set( &heir->is_executing ) ) { |
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| 110 | * do { |
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| 111 | * Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot(); |
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| 112 | * |
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| 113 | * if ( cpu_self->dispatch_necessary ) { |
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| 114 | * heir = _Thread_Get_heir_and_make_it_executing( cpu_self ); |
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| 115 | * } |
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| 116 | * } while ( test_and_set( &heir->is_executing ) ); |
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| 117 | * } |
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| 118 | * |
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| 119 | * restore( heir ); |
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| 120 | * } |
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| 121 | * @endcode |
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| 122 | */ |
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| 123 | volatile bool is_executing; |
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| 124 | #endif |
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| 125 | } Context_Control; |
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| 126 | |
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| 127 | #define _CPU_Context_Get_SP( _context ) \ |
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| 128 | (_context)->x[2] |
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| 129 | |
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| 130 | typedef struct { |
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| 131 | /** TODO FPU registers are listed here */ |
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| 132 | double some_float_register; |
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| 133 | } Context_Control_fp; |
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| 134 | |
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| 135 | typedef Context_Control CPU_Interrupt_frame; |
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| 136 | |
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| 137 | #define CPU_CONTEXT_FP_SIZE 0 |
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| 138 | Context_Control_fp _CPU_Null_fp_context; |
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| 139 | |
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| 140 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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[11ff3a9] | 141 | #if __riscv_xlen == 32 |
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[660db8c8] | 142 | #define CPU_STACK_MINIMUM_SIZE 4096 |
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[11ff3a9] | 143 | #else |
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| 144 | #define CPU_STACK_MINIMUM_SIZE 4096 * 2 |
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| 145 | #endif |
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[660db8c8] | 146 | #define CPU_ALIGNMENT 8 |
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| 147 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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| 148 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 149 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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| 150 | #define CPU_STACK_ALIGNMENT 8 |
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| 151 | #define _CPU_Initialize_vectors() |
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| 152 | |
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| 153 | /* |
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| 154 | * Disable all interrupts for an RTEMS critical section. The previous |
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| 155 | * level is returned in _level. |
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| 156 | * |
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| 157 | */ |
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| 158 | |
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[11ff3a9] | 159 | static inline unsigned long riscv_interrupt_disable( void ) |
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[660db8c8] | 160 | { |
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[11ff3a9] | 161 | register unsigned long status = read_csr(mstatus); |
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[660db8c8] | 162 | clear_csr(mstatus, MSTATUS_MIE); |
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| 163 | return status; |
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| 164 | } |
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| 165 | |
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[11ff3a9] | 166 | static inline void riscv_interrupt_enable(unsigned long level) |
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[660db8c8] | 167 | { |
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| 168 | write_csr(mstatus, level); |
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| 169 | } |
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| 170 | |
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| 171 | #define _CPU_ISR_Disable( _level ) \ |
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| 172 | _level = riscv_interrupt_disable() |
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| 173 | |
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| 174 | #define _CPU_ISR_Enable( _level ) \ |
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| 175 | riscv_interrupt_enable( _level ) |
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| 176 | |
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| 177 | #define _CPU_ISR_Flash( _level ) \ |
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| 178 | do{ \ |
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| 179 | _CPU_ISR_Enable( _level ); \ |
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| 180 | riscv_interrupt_disable(); \ |
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| 181 | } while(0) |
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| 182 | |
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[11ff3a9] | 183 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level ) |
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[660db8c8] | 184 | { |
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| 185 | return ( level & MSTATUS_MIE ) != 0; |
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| 186 | } |
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| 187 | |
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[11ff3a9] | 188 | void _CPU_ISR_Set_level( unsigned long level ); |
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[660db8c8] | 189 | |
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[11ff3a9] | 190 | unsigned long _CPU_ISR_Get_level( void ); |
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[660db8c8] | 191 | |
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| 192 | /* end of ISR handler macros */ |
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| 193 | |
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| 194 | /* Context handler macros */ |
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| 195 | #define RISCV_GCC_RED_ZONE_SIZE 128 |
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| 196 | |
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| 197 | void _CPU_Context_Initialize( |
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| 198 | Context_Control *context, |
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| 199 | void *stack_area_begin, |
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| 200 | size_t stack_area_size, |
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[11ff3a9] | 201 | unsigned long new_level, |
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[660db8c8] | 202 | void (*entry_point)( void ), |
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| 203 | bool is_fp, |
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| 204 | void *tls_area |
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| 205 | ); |
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| 206 | |
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| 207 | #define _CPU_Context_Restart_self( _the_context ) \ |
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| 208 | _CPU_Context_restore( (_the_context) ) |
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| 209 | |
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| 210 | |
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| 211 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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| 212 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
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| 213 | |
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| 214 | #define _CPU_Context_Initialize_fp( _destination ) \ |
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| 215 | { \ |
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| 216 | *(*(_destination)) = _CPU_Null_fp_context; \ |
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| 217 | } |
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| 218 | |
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| 219 | extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) |
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| 220 | RTEMS_NO_RETURN; |
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| 221 | |
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| 222 | /* end of Fatal Error manager macros */ |
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| 223 | |
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| 224 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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| 225 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
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| 226 | |
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| 227 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
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| 228 | |
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| 229 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 230 | { \ |
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| 231 | (_output) = 0; /* do something to prevent warnings */ \ |
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| 232 | } |
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| 233 | #endif |
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| 234 | |
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| 235 | /* end of Bitfield handler macros */ |
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| 236 | |
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| 237 | /* |
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| 238 | * This routine builds the mask which corresponds to the bit fields |
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| 239 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
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| 240 | * for that routine. |
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| 241 | * |
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| 242 | */ |
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| 243 | |
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| 244 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
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| 245 | |
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| 246 | #define _CPU_Priority_Mask( _bit_number ) \ |
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| 247 | (1 << _bit_number) |
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| 248 | |
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| 249 | #endif |
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| 250 | |
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| 251 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
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| 252 | |
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| 253 | #define _CPU_Priority_bits_index( _priority ) \ |
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| 254 | (_priority) |
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| 255 | |
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| 256 | #endif |
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| 257 | |
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| 258 | #define CPU_MAXIMUM_PROCESSORS 32 |
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| 259 | |
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| 260 | #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE |
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| 261 | #define CPU_TIMESTAMP_USE_INT64 TRUE |
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| 262 | #define CPU_TIMESTAMP_USE_INT64_INLINE FALSE |
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| 263 | |
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| 264 | typedef struct { |
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| 265 | /* There is no CPU specific per-CPU state */ |
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| 266 | } CPU_Per_CPU_control; |
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| 267 | #endif /* ASM */ |
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| 268 | |
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[11ff3a9] | 269 | #if __riscv_xlen == 32 |
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[660db8c8] | 270 | #define CPU_SIZEOF_POINTER 4 |
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[11ff3a9] | 271 | |
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| 272 | /* 32-bit load/store instructions */ |
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| 273 | #define LREG lw |
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| 274 | #define SREG sw |
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| 275 | |
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[660db8c8] | 276 | #define CPU_EXCEPTION_FRAME_SIZE 128 |
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[11ff3a9] | 277 | #else /* xlen = 64 */ |
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| 278 | #define CPU_SIZEOF_POINTER 8 |
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| 279 | |
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| 280 | /* 64-bit load/store instructions */ |
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| 281 | #define LREG ld |
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| 282 | #define SREG sd |
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| 283 | |
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| 284 | #define CPU_EXCEPTION_FRAME_SIZE 256 |
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| 285 | #endif |
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| 286 | |
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[660db8c8] | 287 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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| 288 | |
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| 289 | #ifndef ASM |
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| 290 | typedef uint16_t Priority_bit_map_Word; |
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| 291 | |
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| 292 | typedef struct { |
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[11ff3a9] | 293 | unsigned long x[32];; |
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[660db8c8] | 294 | } CPU_Exception_frame; |
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| 295 | |
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| 296 | /** |
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| 297 | * @brief Prints the exception frame via printk(). |
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| 298 | * |
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| 299 | * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. |
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| 300 | */ |
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| 301 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
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| 302 | |
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| 303 | |
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| 304 | /* end of Priority handler macros */ |
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| 305 | |
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| 306 | /* functions */ |
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| 307 | |
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| 308 | /* |
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| 309 | * _CPU_Initialize |
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| 310 | * |
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| 311 | * This routine performs CPU dependent initialization. |
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| 312 | * |
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| 313 | */ |
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| 314 | |
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| 315 | void _CPU_Initialize( |
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| 316 | void |
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| 317 | ); |
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| 318 | |
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| 319 | /* |
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| 320 | * _CPU_ISR_install_raw_handler |
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| 321 | * |
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| 322 | * This routine installs a "raw" interrupt handler directly into the |
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| 323 | * processor's vector table. |
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| 324 | * |
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| 325 | */ |
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| 326 | |
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| 327 | void _CPU_ISR_install_raw_handler( |
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| 328 | uint32_t vector, |
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| 329 | proc_ptr new_handler, |
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| 330 | proc_ptr *old_handler |
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| 331 | ); |
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| 332 | |
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| 333 | /* |
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| 334 | * _CPU_ISR_install_vector |
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| 335 | * |
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| 336 | * This routine installs an interrupt vector. |
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| 337 | * |
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| 338 | * NO_CPU Specific Information: |
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| 339 | * |
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| 340 | * XXX document implementation including references if appropriate |
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| 341 | */ |
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| 342 | |
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| 343 | void _CPU_ISR_install_vector( |
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[11ff3a9] | 344 | unsigned long vector, |
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[660db8c8] | 345 | proc_ptr new_handler, |
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| 346 | proc_ptr *old_handler |
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| 347 | ); |
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| 348 | |
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| 349 | /* |
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| 350 | * _CPU_Install_interrupt_stack |
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| 351 | * |
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| 352 | * This routine installs the hardware interrupt stack pointer. |
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| 353 | * |
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| 354 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
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| 355 | * is TRUE. |
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| 356 | * |
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| 357 | */ |
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| 358 | |
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| 359 | void _CPU_Install_interrupt_stack( void ); |
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| 360 | |
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| 361 | /* |
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| 362 | * _CPU_Thread_Idle_body |
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| 363 | * |
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| 364 | * This routine is the CPU dependent IDLE thread body. |
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| 365 | * |
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| 366 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
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| 367 | * is TRUE. |
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| 368 | * |
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| 369 | */ |
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| 370 | |
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| 371 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
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| 372 | |
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| 373 | /* |
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| 374 | * _CPU_Context_switch |
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| 375 | * |
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| 376 | * This routine switches from the run context to the heir context. |
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| 377 | * |
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| 378 | * RISCV Specific Information: |
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| 379 | * |
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| 380 | * Please see the comments in the .c file for a description of how |
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| 381 | * this function works. There are several things to be aware of. |
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| 382 | */ |
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| 383 | |
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| 384 | void _CPU_Context_switch( |
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| 385 | Context_Control *run, |
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| 386 | Context_Control *heir |
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| 387 | ); |
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| 388 | |
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| 389 | /* |
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| 390 | * _CPU_Context_restore |
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| 391 | * |
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| 392 | * This routine is generally used only to restart self in an |
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| 393 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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| 394 | * |
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| 395 | * NOTE: May be unnecessary to reload some registers. |
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| 396 | * |
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| 397 | */ |
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| 398 | |
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| 399 | void _CPU_Context_restore( |
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| 400 | Context_Control *new_context |
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| 401 | ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
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| 402 | |
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| 403 | /* |
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| 404 | * _CPU_Context_save_fp |
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| 405 | * |
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| 406 | * This routine saves the floating point context passed to it. |
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| 407 | * |
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| 408 | */ |
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| 409 | |
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| 410 | void _CPU_Context_save_fp( |
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| 411 | void **fp_context_ptr |
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| 412 | ); |
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| 413 | |
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| 414 | /* |
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| 415 | * _CPU_Context_restore_fp |
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| 416 | * |
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| 417 | * This routine restores the floating point context passed to it. |
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| 418 | * |
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| 419 | */ |
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| 420 | |
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| 421 | void _CPU_Context_restore_fp( |
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| 422 | void **fp_context_ptr |
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| 423 | ); |
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| 424 | |
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| 425 | /* The following routine swaps the endian format of an unsigned int. |
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| 426 | * It must be static because it is referenced indirectly. |
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| 427 | * |
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| 428 | * This version will work on any processor, but if there is a better |
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| 429 | * way for your CPU PLEASE use it. The most common way to do this is to: |
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| 430 | * |
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| 431 | * swap least significant two bytes with 16-bit rotate |
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| 432 | * swap upper and lower 16-bits |
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| 433 | * swap most significant two bytes with 16-bit rotate |
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| 434 | * |
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| 435 | * Some CPUs have special instructions which swap a 32-bit quantity in |
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| 436 | * a single instruction (e.g. i486). It is probably best to avoid |
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| 437 | * an "endian swapping control bit" in the CPU. One good reason is |
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| 438 | * that interrupts would probably have to be disabled to insure that |
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| 439 | * an interrupt does not try to access the same "chunk" with the wrong |
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| 440 | * endian. Another good reason is that on some CPUs, the endian bit |
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| 441 | * endianness for ALL fetches -- both code and data -- so the code |
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| 442 | * will be fetched incorrectly. |
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| 443 | * |
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| 444 | */ |
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| 445 | |
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[11ff3a9] | 446 | static inline uint32_t CPU_swap_u32( |
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| 447 | uint32_t value |
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[660db8c8] | 448 | ) |
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| 449 | { |
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| 450 | uint32_t byte1, byte2, byte3, byte4, swapped; |
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| 451 | |
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| 452 | byte4 = (value >> 24) & 0xff; |
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| 453 | byte3 = (value >> 16) & 0xff; |
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| 454 | byte2 = (value >> 8) & 0xff; |
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| 455 | byte1 = value & 0xff; |
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| 456 | |
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| 457 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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| 458 | return ( swapped ); |
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| 459 | } |
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| 460 | |
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| 461 | #define CPU_swap_u16( value ) \ |
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| 462 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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| 463 | |
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| 464 | static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) |
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| 465 | { |
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| 466 | /* TODO */ |
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| 467 | } |
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| 468 | |
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| 469 | static inline void _CPU_Context_validate( uintptr_t pattern ) |
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| 470 | { |
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| 471 | while (1) { |
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| 472 | /* TODO */ |
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| 473 | } |
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| 474 | } |
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| 475 | |
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| 476 | typedef uint32_t CPU_Counter_ticks; |
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| 477 | |
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| 478 | CPU_Counter_ticks _CPU_Counter_read( void ); |
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| 479 | |
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| 480 | #ifdef RTEMS_SMP |
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| 481 | /** |
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| 482 | * @brief Performs CPU specific SMP initialization in the context of the boot |
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| 483 | * processor. |
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| 484 | * |
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| 485 | * This function is invoked on the boot processor during system |
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| 486 | * initialization. All interrupt stacks are allocated at this point in case |
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| 487 | * the CPU port allocates the interrupt stacks. This function is called |
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| 488 | * before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is |
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| 489 | * used. |
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| 490 | * |
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| 491 | * @return The count of physically or virtually available processors. |
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| 492 | * Depending on the configuration the application may use not all processors. |
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| 493 | */ |
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| 494 | uint32_t _CPU_SMP_Initialize( void ); |
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| 495 | |
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| 496 | /** |
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| 497 | * @brief Starts a processor specified by its index. |
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| 498 | * |
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| 499 | * This function is invoked on the boot processor during system |
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| 500 | * initialization. |
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| 501 | * |
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| 502 | * This function will be called after _CPU_SMP_Initialize(). |
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| 503 | * |
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| 504 | * @param[in] cpu_index The processor index. |
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| 505 | * |
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| 506 | * @retval true Successful operation. |
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| 507 | * @retval false Unable to start this processor. |
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| 508 | */ |
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| 509 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
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| 510 | |
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| 511 | /** |
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| 512 | * @brief Performs final steps of CPU specific SMP initialization in the |
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| 513 | * context of the boot processor. |
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| 514 | * |
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| 515 | * This function is invoked on the boot processor during system |
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| 516 | * initialization. |
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| 517 | * |
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| 518 | * This function will be called after all processors requested by the |
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| 519 | * application have been started. |
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| 520 | * |
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| 521 | * @param[in] cpu_count The minimum value of the count of processors |
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| 522 | * requested by the application configuration and the count of physically or |
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| 523 | * virtually available processors. |
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| 524 | */ |
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| 525 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
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| 526 | |
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| 527 | /** |
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| 528 | * @brief Returns the index of the current processor. |
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| 529 | * |
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| 530 | * An architecture specific method must be used to obtain the index of the |
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| 531 | * current processor in the system. The set of processor indices is the |
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| 532 | * range of integers starting with zero up to the processor count minus one. |
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| 533 | */ |
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| 534 | uint32_t _CPU_SMP_Get_current_processor( void ); |
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| 535 | |
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| 536 | /** |
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| 537 | * @brief Sends an inter-processor interrupt to the specified target |
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| 538 | * processor. |
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| 539 | * |
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| 540 | * This operation is undefined for target processor indices out of range. |
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| 541 | * |
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| 542 | * @param[in] target_processor_index The target processor index. |
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| 543 | */ |
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| 544 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
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| 545 | |
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| 546 | /** |
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| 547 | * @brief Broadcasts a processor event. |
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| 548 | * |
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| 549 | * Some architectures provide a low-level synchronization primitive for |
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| 550 | * processors in a multi-processor environment. Processors waiting for this |
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| 551 | * event may go into a low-power state and stop generating system bus |
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| 552 | * transactions. This function must ensure that preceding store operations |
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| 553 | * can be observed by other processors. |
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| 554 | * |
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| 555 | * @see _CPU_SMP_Processor_event_receive(). |
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| 556 | */ |
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| 557 | void _CPU_SMP_Processor_event_broadcast( void ); |
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| 558 | |
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| 559 | /** |
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| 560 | * @brief Receives a processor event. |
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| 561 | * |
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| 562 | * This function will wait for the processor event and may wait forever if no |
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| 563 | * such event arrives. |
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| 564 | * |
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| 565 | * @see _CPU_SMP_Processor_event_broadcast(). |
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| 566 | */ |
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| 567 | static inline void _CPU_SMP_Processor_event_receive( void ) |
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| 568 | { |
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| 569 | __asm__ volatile ( "" : : : "memory" ); |
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| 570 | } |
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| 571 | |
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| 572 | /** |
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| 573 | * @brief Gets the is executing indicator of the thread context. |
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| 574 | * |
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| 575 | * @param[in] context The context. |
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| 576 | */ |
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| 577 | static inline bool _CPU_Context_Get_is_executing( |
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| 578 | const Context_Control *context |
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| 579 | ) |
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| 580 | { |
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| 581 | return context->is_executing; |
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| 582 | } |
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| 583 | |
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| 584 | /** |
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| 585 | * @brief Sets the is executing indicator of the thread context. |
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| 586 | * |
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| 587 | * @param[in] context The context. |
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| 588 | * @param[in] is_executing The new value for the is executing indicator. |
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| 589 | */ |
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| 590 | static inline void _CPU_Context_Set_is_executing( |
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| 591 | Context_Control *context, |
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| 592 | bool is_executing |
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| 593 | ) |
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| 594 | { |
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| 595 | context->is_executing = is_executing; |
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| 596 | } |
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| 597 | #endif /* RTEMS_SMP */ |
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| 598 | |
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| 599 | #endif /* ASM */ |
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| 600 | |
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| 601 | #ifdef __cplusplus |
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| 602 | } |
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| 603 | #endif |
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| 604 | |
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| 605 | #endif |
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