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riscv-exception-handler.S @ 7c3b0df1

Last change on this file since 7c3b0df1 was 52f4fb6, checked in by Sebastian Huber <sebastian.huber@…>, on 06/26/18 at 05:48:06

riscv: Format assembler files

Use tabs to match the GCC generated assembler output.

Update #3433.

Property mode set to 100644

File size: 6.3 KB

Line
1	/**
2	* @file
3	*
4	* @ingroup ScoreCPU
5	*
6	* @brief RISC-V exception support implementation.
7	*/
8
9	/*
10	* Copyright (c) 2015 University of York.
11	* Hesham Almatary <hesham@alumni.york.ac.uk>
12	*
13	* Redistribution and use in source and binary forms, with or without
14	* modification, are permitted provided that the following conditions
15	* are met:
16	* 1. Redistributions of source code must retain the above copyright
17	* notice, this list of conditions and the following disclaimer.
18	* 2. Redistributions in binary form must reproduce the above copyright
19	* notice, this list of conditions and the following disclaimer in the
20	* documentation and/or other materials provided with the distribution.
21	*
22	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32	* SUCH DAMAGE.
33	*/
34
35	#ifdef HAVE_CONFIG_H
36	#include "config.h"
37	#endif
38
39	#include <rtems/score/cpu.h>
40
41	#include <rtems/asm.h>
42	#include <rtems/score/percpu.h>
43
44	EXTERN(bsp_start_vector_table_begin)
45	EXTERN(_Thread_Dispatch)
46	PUBLIC(ISR_Handler)
47
48	.section .text, "ax", @progbits
49	.align 2
50
51	TYPE_FUNC(ISR_Handler)
52	SYM(ISR_Handler):
53	addi sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
54
55	SREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
56	/* Skip x2/sp */
57	SREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
58	SREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
59	SREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
60	SREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
61	SREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
62	SREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
63	SREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
64	SREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
65	SREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
66	SREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
67	SREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
68	SREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
69	SREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
70	SREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
71	SREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
72	SREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
73	SREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
74	SREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
75	SREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
76	SREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
77	SREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
78	SREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
79	SREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
80	SREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
81	SREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
82	SREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
83	SREG x29, (28 * CPU_SIZEOF_POINTER)(sp)
84	SREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
85	SREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
86
87	/* Exception level related registers */
88	csrr a0, mstatus
89	SREG a0, (32 * CPU_SIZEOF_POINTER)(sp)
90	csrr a0, mcause
91	SREG a0, (33 * CPU_SIZEOF_POINTER)(sp)
92	csrr a1, mepc
93	SREG a1, (34 * CPU_SIZEOF_POINTER)(sp)
94
95	/* FIXME Only handle interrupts for now (MSB = 1) */
96	andi a0, a0, 0xf
97
98	/* Increment nesting level */
99	la t0, ISR_NEST_LEVEL
100
101	/* Disable multitasking */
102	la t1, THREAD_DISPATCH_DISABLE_LEVEL
103
104	lw t2, (t0)
105	lw t3, (t1)
106	addi t2, t2, 1
107	addi t3, t3, 1
108	sw t2, (t0)
109	sw t3, (t1)
110
111	/* Save interrupted task stack pointer */
112	addi t4, sp, 36 * CPU_SIZEOF_POINTER
113	SREG t4, (2 * CPU_SIZEOF_POINTER)(sp)
114
115	/* Keep sp (Exception frame address) in s1 */
116	mv s1, sp
117
118	/* Call the exception handler from vector table */
119
120	/* First function arg for C handler is vector number,
121	* and the second is a pointer to exception frame.
122	* a0/mcause/vector number is already loaded above */
123	mv a1, sp
124
125	/* calculate the offset */
126	la t5, bsp_start_vector_table_begin
127	#if __riscv_xlen == 32
128	slli t6, a0, 2
129	#else /* xlen = 64 */
130	slli t6, a0, 3
131	#endif
132	add t5, t5, t6
133	LREG t5, (t5)
134
135	/* Do not switch stacks if we are in a nested interrupt. At
136	* this point t2 should be holding ISR_NEST_LEVEL value.
137	*/
138	li s0, 1
139	bgtu t2, s0, jump_to_c_handler
140
141	/* Switch to RTEMS dedicated interrupt stack */
142	la sp, INTERRUPT_STACK_HIGH
143	LREG sp, (sp)
144
145	jump_to_c_handler:
146	jalr t5
147
148	/* Switch back to the interrupted task stack */
149	mv sp, s1
150
151	/* Decrement nesting level */
152	la t0, ISR_NEST_LEVEL
153
154	/* Enable multitasking */
155	la t1, THREAD_DISPATCH_DISABLE_LEVEL
156
157	Lw t2, (t0)
158	lw t3, (t1)
159	addi t2, t2, -1
160	addi t3, t3, -1
161	sw t2, (t0)
162	sw t3, (t1)
163
164	/* Check if _ISR_Nest_level > 0 */
165	bgtz t2, exception_frame_restore
166
167	/* Check if _Thread_Dispatch_disable_level > 0 */
168	bgtz t3, exception_frame_restore
169
170	/* Check if dispatch needed */
171	la x31, DISPATCH_NEEDED
172	lw x31, (x31)
173	beqz x31, exception_frame_restore
174
175	la x31, _Thread_Dispatch
176	jalr x31
177
178	SYM(exception_frame_restore):
179	LREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
180	/* Skip sp/x2 */
181	LREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
182	LREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
183	LREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
184	LREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
185	LREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
186	LREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
187	LREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
188	LREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
189	LREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
190	LREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
191	LREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
192	LREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
193	LREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
194	LREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
195	LREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
196	LREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
197	LREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
198	LREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
199	LREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
200	LREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
201	LREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
202	LREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
203	LREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
204	LREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
205	LREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
206	LREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
207	LREG x29, (29 * CPU_SIZEOF_POINTER)(sp)
208	LREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
209
210	/* Load mstatus */
211	LREG x31, (32 * CPU_SIZEOF_POINTER)(sp)
212	csrw mstatus, x31
213	/* Load mepc */
214	LREG x31, (34 * CPU_SIZEOF_POINTER)(sp)
215	csrw mepc, x31
216
217	LREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
218
219	/* Unwind exception frame */
220	addi sp, sp, 36 * CPU_SIZEOF_POINTER
221
222	mret

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