1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup ScoreCPU |
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5 | * |
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6 | * @brief RISC-V exception support implementation. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2018 embedded brains GmbH |
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11 | |
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12 | * Copyright (c) 2015 University of York. |
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13 | * Hesham Almatary <hesham@alumni.york.ac.uk> |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions |
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17 | * are met: |
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18 | * 1. Redistributions of source code must retain the above copyright |
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19 | * notice, this list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright |
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21 | * notice, this list of conditions and the following disclaimer in the |
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22 | * documentation and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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30 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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31 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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32 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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33 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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34 | * SUCH DAMAGE. |
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35 | */ |
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36 | |
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37 | #ifdef HAVE_CONFIG_H |
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38 | #include "config.h" |
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39 | #endif |
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40 | |
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41 | #include <rtems/asm.h> |
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42 | #include <rtems/score/percpu.h> |
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43 | |
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44 | EXTERN(bsp_start_vector_table_begin) |
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45 | EXTERN(_Thread_Dispatch) |
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46 | PUBLIC(ISR_Handler) |
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47 | |
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48 | .section .text, "ax", @progbits |
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49 | .align 2 |
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50 | |
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51 | TYPE_FUNC(ISR_Handler) |
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52 | SYM(ISR_Handler): |
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53 | addi sp, sp, -CPU_INTERRUPT_FRAME_SIZE |
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54 | |
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55 | /* Save */ |
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56 | SREG a0, RISCV_INTERRUPT_FRAME_A0(sp) |
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57 | SREG a1, RISCV_INTERRUPT_FRAME_A1(sp) |
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58 | SREG a2, RISCV_INTERRUPT_FRAME_A2(sp) |
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59 | SREG s0, RISCV_INTERRUPT_FRAME_S0(sp) |
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60 | csrr a0, mcause |
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61 | csrr a1, mstatus |
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62 | csrr a2, mepc |
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63 | GET_SELF_CPU_CONTROL s0 |
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64 | SREG s1, RISCV_INTERRUPT_FRAME_S1(sp) |
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65 | #if __riscv_flen > 0 |
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66 | frcsr s1 |
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67 | #endif |
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68 | SREG ra, RISCV_INTERRUPT_FRAME_RA(sp) |
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69 | SREG a3, RISCV_INTERRUPT_FRAME_A3(sp) |
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70 | SREG a4, RISCV_INTERRUPT_FRAME_A4(sp) |
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71 | SREG a5, RISCV_INTERRUPT_FRAME_A5(sp) |
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72 | SREG a6, RISCV_INTERRUPT_FRAME_A6(sp) |
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73 | SREG a7, RISCV_INTERRUPT_FRAME_A7(sp) |
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74 | SREG t0, RISCV_INTERRUPT_FRAME_T0(sp) |
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75 | SREG t1, RISCV_INTERRUPT_FRAME_T1(sp) |
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76 | SREG t2, RISCV_INTERRUPT_FRAME_T2(sp) |
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77 | SREG t3, RISCV_INTERRUPT_FRAME_T3(sp) |
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78 | SREG t4, RISCV_INTERRUPT_FRAME_T4(sp) |
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79 | SREG t5, RISCV_INTERRUPT_FRAME_T5(sp) |
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80 | SREG t6, RISCV_INTERRUPT_FRAME_T6(sp) |
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81 | SREG a1, RISCV_INTERRUPT_FRAME_MSTATUS(sp) |
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82 | SREG a2, RISCV_INTERRUPT_FRAME_MEPC(sp) |
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83 | #if __riscv_flen > 0 |
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84 | sw s1, RISCV_INTERRUPT_FRAME_FCSR(sp) |
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85 | FSREG ft0, RISCV_INTERRUPT_FRAME_FT0(sp) |
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86 | FSREG ft1, RISCV_INTERRUPT_FRAME_FT1(sp) |
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87 | FSREG ft2, RISCV_INTERRUPT_FRAME_FT2(sp) |
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88 | FSREG ft3, RISCV_INTERRUPT_FRAME_FT3(sp) |
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89 | FSREG ft4, RISCV_INTERRUPT_FRAME_FT4(sp) |
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90 | FSREG ft5, RISCV_INTERRUPT_FRAME_FT5(sp) |
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91 | FSREG ft6, RISCV_INTERRUPT_FRAME_FT6(sp) |
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92 | FSREG ft7, RISCV_INTERRUPT_FRAME_FT7(sp) |
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93 | FSREG ft8, RISCV_INTERRUPT_FRAME_FT8(sp) |
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94 | FSREG ft9, RISCV_INTERRUPT_FRAME_FT9(sp) |
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95 | FSREG ft10, RISCV_INTERRUPT_FRAME_FT10(sp) |
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96 | FSREG ft11, RISCV_INTERRUPT_FRAME_FT11(sp) |
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97 | FSREG fa0, RISCV_INTERRUPT_FRAME_FA0(sp) |
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98 | FSREG fa1, RISCV_INTERRUPT_FRAME_FA1(sp) |
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99 | FSREG fa2, RISCV_INTERRUPT_FRAME_FA2(sp) |
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100 | FSREG fa3, RISCV_INTERRUPT_FRAME_FA3(sp) |
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101 | FSREG fa4, RISCV_INTERRUPT_FRAME_FA4(sp) |
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102 | FSREG fa5, RISCV_INTERRUPT_FRAME_FA5(sp) |
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103 | FSREG fa6, RISCV_INTERRUPT_FRAME_FA6(sp) |
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104 | FSREG fa7, RISCV_INTERRUPT_FRAME_FA7(sp) |
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105 | #endif |
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106 | |
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107 | /* FIXME Only handle interrupts for now (MSB = 1) */ |
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108 | andi a0, a0, 0xf |
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109 | |
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110 | /* Increment interrupt nest and thread dispatch disable level */ |
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111 | lw t0, PER_CPU_ISR_NEST_LEVEL(s0) |
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112 | lw t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0) |
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113 | addi t2, t0, 1 |
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114 | addi t1, t1, 1 |
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115 | sw t2, PER_CPU_ISR_NEST_LEVEL(s0) |
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116 | sw t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0) |
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117 | |
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118 | CLEAR_RESERVATIONS s0 |
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119 | |
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120 | /* Keep sp (Exception frame address) in s1 */ |
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121 | mv s1, sp |
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122 | |
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123 | /* Call the exception handler from vector table */ |
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124 | |
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125 | /* First function arg for C handler is vector number, |
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126 | * and the second is a pointer to exception frame. |
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127 | * a0/mcause/vector number is already loaded above */ |
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128 | mv a1, sp |
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129 | |
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130 | /* calculate the offset */ |
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131 | LADDR t5, bsp_start_vector_table_begin |
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132 | #if __riscv_xlen == 32 |
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133 | slli t6, a0, 2 |
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134 | #else /* xlen = 64 */ |
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135 | slli t6, a0, 3 |
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136 | #endif |
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137 | add t5, t5, t6 |
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138 | LREG t5, (t5) |
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139 | |
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140 | /* Switch to interrupt stack if necessary */ |
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141 | bnez t0, .Linterrupt_stack_switch_done |
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142 | LREG sp, PER_CPU_INTERRUPT_STACK_HIGH(s0) |
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143 | .Linterrupt_stack_switch_done: |
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144 | |
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145 | jalr t5 |
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146 | |
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147 | /* Load some per-CPU variables */ |
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148 | lw t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0) |
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149 | lbu t1, PER_CPU_DISPATCH_NEEDED(s0) |
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150 | lw t2, PER_CPU_ISR_DISPATCH_DISABLE(s0) |
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151 | lw t3, PER_CPU_ISR_NEST_LEVEL(s0) |
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152 | |
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153 | /* Restore stack pointer */ |
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154 | mv sp, s1 |
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155 | |
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156 | /* Decrement levels and determine thread dispatch state */ |
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157 | xor t1, t1, t0 |
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158 | addi t0, t0, -1 |
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159 | or t1, t1, t0 |
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160 | or t1, t1, t2 |
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161 | addi t3, t3, -1 |
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162 | |
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163 | /* Store thread dispatch disable and ISR nest levels */ |
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164 | sw t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0) |
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165 | sw t3, PER_CPU_ISR_NEST_LEVEL(s0) |
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166 | |
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167 | /* |
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168 | * Check thread dispatch necessary, ISR dispatch disable and thread |
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169 | * dispatch disable level. |
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170 | */ |
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171 | bnez t1, .Lthread_dispatch_done |
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172 | |
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173 | .Ldo_thread_dispatch: |
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174 | |
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175 | /* Set ISR dispatch disable and thread dispatch disable level to one */ |
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176 | li t0, 1 |
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177 | sw t0, PER_CPU_ISR_DISPATCH_DISABLE(s0) |
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178 | sw t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0) |
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179 | |
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180 | /* Call _Thread_Do_dispatch(), this function will enable interrupts */ |
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181 | mv a0, s0 |
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182 | li a1, RISCV_MSTATUS_MIE |
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183 | call _Thread_Do_dispatch |
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184 | |
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185 | /* Disable interrupts */ |
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186 | csrrc zero, mstatus, RISCV_MSTATUS_MIE |
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187 | |
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188 | #ifdef RTEMS_SMP |
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189 | GET_SELF_CPU_CONTROL s0 |
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190 | #endif |
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191 | |
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192 | /* Check if we have to do the thread dispatch again */ |
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193 | lbu t0, PER_CPU_DISPATCH_NEEDED(s0) |
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194 | bnez t0, .Ldo_thread_dispatch |
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195 | |
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196 | /* We are done with thread dispatching */ |
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197 | sw zero, PER_CPU_ISR_DISPATCH_DISABLE(s0) |
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198 | |
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199 | .Lthread_dispatch_done: |
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200 | |
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201 | /* Restore */ |
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202 | LREG a0, RISCV_INTERRUPT_FRAME_MSTATUS(sp) |
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203 | LREG a1, RISCV_INTERRUPT_FRAME_MEPC(sp) |
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204 | LREG a2, RISCV_INTERRUPT_FRAME_A2(sp) |
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205 | LREG s0, RISCV_INTERRUPT_FRAME_S0(sp) |
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206 | LREG s1, RISCV_INTERRUPT_FRAME_S1(sp) |
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207 | LREG ra, RISCV_INTERRUPT_FRAME_RA(sp) |
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208 | LREG a3, RISCV_INTERRUPT_FRAME_A3(sp) |
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209 | LREG a4, RISCV_INTERRUPT_FRAME_A4(sp) |
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210 | LREG a5, RISCV_INTERRUPT_FRAME_A5(sp) |
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211 | LREG a6, RISCV_INTERRUPT_FRAME_A6(sp) |
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212 | LREG a7, RISCV_INTERRUPT_FRAME_A7(sp) |
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213 | LREG t0, RISCV_INTERRUPT_FRAME_T0(sp) |
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214 | LREG t1, RISCV_INTERRUPT_FRAME_T1(sp) |
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215 | LREG t2, RISCV_INTERRUPT_FRAME_T2(sp) |
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216 | LREG t3, RISCV_INTERRUPT_FRAME_T3(sp) |
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217 | LREG t4, RISCV_INTERRUPT_FRAME_T4(sp) |
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218 | LREG t5, RISCV_INTERRUPT_FRAME_T5(sp) |
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219 | LREG t6, RISCV_INTERRUPT_FRAME_T6(sp) |
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220 | csrw mstatus, a0 |
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221 | csrw mepc, a1 |
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222 | #if __riscv_flen > 0 |
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223 | lw a0, RISCV_INTERRUPT_FRAME_FCSR(sp) |
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224 | FLREG ft0, RISCV_INTERRUPT_FRAME_FT0(sp) |
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225 | FLREG ft1, RISCV_INTERRUPT_FRAME_FT1(sp) |
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226 | FLREG ft2, RISCV_INTERRUPT_FRAME_FT2(sp) |
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227 | FLREG ft3, RISCV_INTERRUPT_FRAME_FT3(sp) |
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228 | FLREG ft4, RISCV_INTERRUPT_FRAME_FT4(sp) |
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229 | FLREG ft5, RISCV_INTERRUPT_FRAME_FT5(sp) |
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230 | FLREG ft6, RISCV_INTERRUPT_FRAME_FT6(sp) |
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231 | FLREG ft7, RISCV_INTERRUPT_FRAME_FT7(sp) |
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232 | FLREG ft8, RISCV_INTERRUPT_FRAME_FT8(sp) |
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233 | FLREG ft9, RISCV_INTERRUPT_FRAME_FT9(sp) |
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234 | FLREG ft10, RISCV_INTERRUPT_FRAME_FT10(sp) |
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235 | FLREG ft11, RISCV_INTERRUPT_FRAME_FT11(sp) |
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236 | FLREG fa0, RISCV_INTERRUPT_FRAME_FA0(sp) |
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237 | FLREG fa1, RISCV_INTERRUPT_FRAME_FA1(sp) |
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238 | FLREG fa2, RISCV_INTERRUPT_FRAME_FA2(sp) |
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239 | FLREG fa3, RISCV_INTERRUPT_FRAME_FA3(sp) |
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240 | FLREG fa4, RISCV_INTERRUPT_FRAME_FA4(sp) |
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241 | FLREG fa5, RISCV_INTERRUPT_FRAME_FA5(sp) |
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242 | FLREG fa6, RISCV_INTERRUPT_FRAME_FA6(sp) |
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243 | FLREG fa7, RISCV_INTERRUPT_FRAME_FA7(sp) |
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244 | fscsr a0 |
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245 | #endif |
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246 | LREG a0, RISCV_INTERRUPT_FRAME_A0(sp) |
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247 | LREG a1, RISCV_INTERRUPT_FRAME_A1(sp) |
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248 | |
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249 | addi sp, sp, CPU_INTERRUPT_FRAME_SIZE |
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250 | |
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251 | mret |
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