[660db8c8] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup ScoreCPU |
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| 5 | * |
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[11ff3a9] | 6 | * @brief RISC-V exception support implementation. |
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[660db8c8] | 7 | */ |
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| 8 | |
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| 9 | /* |
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[9704d86f] | 10 | * Copyright (c) 2018 embedded brains GmbH |
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| 11 | |
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[660db8c8] | 12 | * Copyright (c) 2015 University of York. |
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| 13 | * Hesham Almatary <hesham@alumni.york.ac.uk> |
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| 14 | * |
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| 15 | * Redistribution and use in source and binary forms, with or without |
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| 16 | * modification, are permitted provided that the following conditions |
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| 17 | * are met: |
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| 18 | * 1. Redistributions of source code must retain the above copyright |
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| 19 | * notice, this list of conditions and the following disclaimer. |
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| 20 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 21 | * notice, this list of conditions and the following disclaimer in the |
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| 22 | * documentation and/or other materials provided with the distribution. |
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| 23 | * |
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| 24 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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| 25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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| 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 30 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 31 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 32 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 33 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 34 | * SUCH DAMAGE. |
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| 35 | */ |
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| 36 | |
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| 37 | #ifdef HAVE_CONFIG_H |
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| 38 | #include "config.h" |
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| 39 | #endif |
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| 40 | |
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| 41 | #include <rtems/asm.h> |
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| 42 | #include <rtems/score/percpu.h> |
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| 43 | |
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[8db3f0e] | 44 | PUBLIC(_RISCV_Exception_handler) |
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[660db8c8] | 45 | |
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[52f4fb6] | 46 | .section .text, "ax", @progbits |
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| 47 | .align 2 |
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| 48 | |
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[8db3f0e] | 49 | TYPE_FUNC(_RISCV_Exception_handler) |
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| 50 | SYM(_RISCV_Exception_handler): |
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[e43994d] | 51 | addi sp, sp, -CPU_INTERRUPT_FRAME_SIZE |
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| 52 | |
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| 53 | /* Save */ |
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| 54 | SREG a0, RISCV_INTERRUPT_FRAME_A0(sp) |
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| 55 | SREG a1, RISCV_INTERRUPT_FRAME_A1(sp) |
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| 56 | SREG a2, RISCV_INTERRUPT_FRAME_A2(sp) |
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| 57 | SREG s0, RISCV_INTERRUPT_FRAME_S0(sp) |
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[52f4fb6] | 58 | csrr a0, mcause |
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[e43994d] | 59 | csrr a1, mstatus |
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| 60 | csrr a2, mepc |
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| 61 | GET_SELF_CPU_CONTROL s0 |
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| 62 | SREG s1, RISCV_INTERRUPT_FRAME_S1(sp) |
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[52352387] | 63 | #if __riscv_flen > 0 |
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| 64 | frcsr s1 |
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| 65 | #endif |
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[e43994d] | 66 | SREG ra, RISCV_INTERRUPT_FRAME_RA(sp) |
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| 67 | SREG a3, RISCV_INTERRUPT_FRAME_A3(sp) |
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| 68 | SREG a4, RISCV_INTERRUPT_FRAME_A4(sp) |
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| 69 | SREG a5, RISCV_INTERRUPT_FRAME_A5(sp) |
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| 70 | SREG a6, RISCV_INTERRUPT_FRAME_A6(sp) |
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| 71 | SREG a7, RISCV_INTERRUPT_FRAME_A7(sp) |
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| 72 | SREG t0, RISCV_INTERRUPT_FRAME_T0(sp) |
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| 73 | SREG t1, RISCV_INTERRUPT_FRAME_T1(sp) |
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| 74 | SREG t2, RISCV_INTERRUPT_FRAME_T2(sp) |
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| 75 | SREG t3, RISCV_INTERRUPT_FRAME_T3(sp) |
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| 76 | SREG t4, RISCV_INTERRUPT_FRAME_T4(sp) |
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| 77 | SREG t5, RISCV_INTERRUPT_FRAME_T5(sp) |
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| 78 | SREG t6, RISCV_INTERRUPT_FRAME_T6(sp) |
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| 79 | SREG a1, RISCV_INTERRUPT_FRAME_MSTATUS(sp) |
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| 80 | SREG a2, RISCV_INTERRUPT_FRAME_MEPC(sp) |
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[52352387] | 81 | #if __riscv_flen > 0 |
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| 82 | sw s1, RISCV_INTERRUPT_FRAME_FCSR(sp) |
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| 83 | FSREG ft0, RISCV_INTERRUPT_FRAME_FT0(sp) |
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| 84 | FSREG ft1, RISCV_INTERRUPT_FRAME_FT1(sp) |
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| 85 | FSREG ft2, RISCV_INTERRUPT_FRAME_FT2(sp) |
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| 86 | FSREG ft3, RISCV_INTERRUPT_FRAME_FT3(sp) |
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| 87 | FSREG ft4, RISCV_INTERRUPT_FRAME_FT4(sp) |
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| 88 | FSREG ft5, RISCV_INTERRUPT_FRAME_FT5(sp) |
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| 89 | FSREG ft6, RISCV_INTERRUPT_FRAME_FT6(sp) |
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| 90 | FSREG ft7, RISCV_INTERRUPT_FRAME_FT7(sp) |
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| 91 | FSREG ft8, RISCV_INTERRUPT_FRAME_FT8(sp) |
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| 92 | FSREG ft9, RISCV_INTERRUPT_FRAME_FT9(sp) |
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| 93 | FSREG ft10, RISCV_INTERRUPT_FRAME_FT10(sp) |
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| 94 | FSREG ft11, RISCV_INTERRUPT_FRAME_FT11(sp) |
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| 95 | FSREG fa0, RISCV_INTERRUPT_FRAME_FA0(sp) |
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| 96 | FSREG fa1, RISCV_INTERRUPT_FRAME_FA1(sp) |
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| 97 | FSREG fa2, RISCV_INTERRUPT_FRAME_FA2(sp) |
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| 98 | FSREG fa3, RISCV_INTERRUPT_FRAME_FA3(sp) |
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| 99 | FSREG fa4, RISCV_INTERRUPT_FRAME_FA4(sp) |
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| 100 | FSREG fa5, RISCV_INTERRUPT_FRAME_FA5(sp) |
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| 101 | FSREG fa6, RISCV_INTERRUPT_FRAME_FA6(sp) |
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| 102 | FSREG fa7, RISCV_INTERRUPT_FRAME_FA7(sp) |
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| 103 | #endif |
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[52f4fb6] | 104 | |
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[8db3f0e] | 105 | /* Check if this is a synchronous or interrupt exception */ |
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| 106 | bgez a0, .Lsynchronous_exception |
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[52f4fb6] | 107 | |
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[9704d86f] | 108 | /* Increment interrupt nest and thread dispatch disable level */ |
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| 109 | lw t0, PER_CPU_ISR_NEST_LEVEL(s0) |
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| 110 | lw t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0) |
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| 111 | addi t2, t0, 1 |
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| 112 | addi t1, t1, 1 |
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| 113 | sw t2, PER_CPU_ISR_NEST_LEVEL(s0) |
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| 114 | sw t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0) |
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[52f4fb6] | 115 | |
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[e755782] | 116 | CLEAR_RESERVATIONS s0 |
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| 117 | |
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[8db3f0e] | 118 | /* |
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| 119 | * Remember current stack pointer in non-volatile register s1. Switch |
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| 120 | * to interrupt stack if necessary. |
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| 121 | */ |
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[52f4fb6] | 122 | mv s1, sp |
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[9704d86f] | 123 | bnez t0, .Linterrupt_stack_switch_done |
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| 124 | LREG sp, PER_CPU_INTERRUPT_STACK_HIGH(s0) |
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| 125 | .Linterrupt_stack_switch_done: |
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[660db8c8] | 126 | |
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[8db3f0e] | 127 | mv a1, s0 |
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| 128 | call _RISCV_Interrupt_dispatch |
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[52f4fb6] | 129 | |
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[9704d86f] | 130 | /* Load some per-CPU variables */ |
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| 131 | lw t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0) |
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| 132 | lbu t1, PER_CPU_DISPATCH_NEEDED(s0) |
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| 133 | lw t2, PER_CPU_ISR_DISPATCH_DISABLE(s0) |
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| 134 | lw t3, PER_CPU_ISR_NEST_LEVEL(s0) |
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| 135 | |
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| 136 | /* Restore stack pointer */ |
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[52f4fb6] | 137 | mv sp, s1 |
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| 138 | |
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[9704d86f] | 139 | /* Decrement levels and determine thread dispatch state */ |
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| 140 | xor t1, t1, t0 |
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| 141 | addi t0, t0, -1 |
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| 142 | or t1, t1, t0 |
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| 143 | or t1, t1, t2 |
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| 144 | addi t3, t3, -1 |
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| 145 | |
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| 146 | /* Store thread dispatch disable and ISR nest levels */ |
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| 147 | sw t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0) |
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| 148 | sw t3, PER_CPU_ISR_NEST_LEVEL(s0) |
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[52f4fb6] | 149 | |
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[9704d86f] | 150 | /* |
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| 151 | * Check thread dispatch necessary, ISR dispatch disable and thread |
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| 152 | * dispatch disable level. |
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| 153 | */ |
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| 154 | bnez t1, .Lthread_dispatch_done |
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[52f4fb6] | 155 | |
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[9704d86f] | 156 | .Ldo_thread_dispatch: |
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| 157 | |
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| 158 | /* Set ISR dispatch disable and thread dispatch disable level to one */ |
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| 159 | li t0, 1 |
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| 160 | sw t0, PER_CPU_ISR_DISPATCH_DISABLE(s0) |
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| 161 | sw t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0) |
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[52f4fb6] | 162 | |
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[9704d86f] | 163 | /* Call _Thread_Do_dispatch(), this function will enable interrupts */ |
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| 164 | mv a0, s0 |
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| 165 | li a1, RISCV_MSTATUS_MIE |
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| 166 | call _Thread_Do_dispatch |
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| 167 | |
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| 168 | /* Disable interrupts */ |
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| 169 | csrrc zero, mstatus, RISCV_MSTATUS_MIE |
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| 170 | |
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| 171 | #ifdef RTEMS_SMP |
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| 172 | GET_SELF_CPU_CONTROL s0 |
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| 173 | #endif |
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[52f4fb6] | 174 | |
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[9704d86f] | 175 | /* Check if we have to do the thread dispatch again */ |
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| 176 | lbu t0, PER_CPU_DISPATCH_NEEDED(s0) |
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| 177 | bnez t0, .Ldo_thread_dispatch |
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[52f4fb6] | 178 | |
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[9704d86f] | 179 | /* We are done with thread dispatching */ |
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| 180 | sw zero, PER_CPU_ISR_DISPATCH_DISABLE(s0) |
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[52f4fb6] | 181 | |
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[9704d86f] | 182 | .Lthread_dispatch_done: |
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[52f4fb6] | 183 | |
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[e43994d] | 184 | /* Restore */ |
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| 185 | LREG a0, RISCV_INTERRUPT_FRAME_MSTATUS(sp) |
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| 186 | LREG a1, RISCV_INTERRUPT_FRAME_MEPC(sp) |
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| 187 | LREG a2, RISCV_INTERRUPT_FRAME_A2(sp) |
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| 188 | LREG s0, RISCV_INTERRUPT_FRAME_S0(sp) |
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| 189 | LREG s1, RISCV_INTERRUPT_FRAME_S1(sp) |
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| 190 | LREG ra, RISCV_INTERRUPT_FRAME_RA(sp) |
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| 191 | LREG a3, RISCV_INTERRUPT_FRAME_A3(sp) |
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| 192 | LREG a4, RISCV_INTERRUPT_FRAME_A4(sp) |
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| 193 | LREG a5, RISCV_INTERRUPT_FRAME_A5(sp) |
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| 194 | LREG a6, RISCV_INTERRUPT_FRAME_A6(sp) |
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| 195 | LREG a7, RISCV_INTERRUPT_FRAME_A7(sp) |
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| 196 | LREG t0, RISCV_INTERRUPT_FRAME_T0(sp) |
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| 197 | LREG t1, RISCV_INTERRUPT_FRAME_T1(sp) |
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| 198 | LREG t2, RISCV_INTERRUPT_FRAME_T2(sp) |
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| 199 | LREG t3, RISCV_INTERRUPT_FRAME_T3(sp) |
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| 200 | LREG t4, RISCV_INTERRUPT_FRAME_T4(sp) |
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| 201 | LREG t5, RISCV_INTERRUPT_FRAME_T5(sp) |
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| 202 | LREG t6, RISCV_INTERRUPT_FRAME_T6(sp) |
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| 203 | csrw mstatus, a0 |
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| 204 | csrw mepc, a1 |
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[52352387] | 205 | #if __riscv_flen > 0 |
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| 206 | lw a0, RISCV_INTERRUPT_FRAME_FCSR(sp) |
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| 207 | FLREG ft0, RISCV_INTERRUPT_FRAME_FT0(sp) |
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| 208 | FLREG ft1, RISCV_INTERRUPT_FRAME_FT1(sp) |
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| 209 | FLREG ft2, RISCV_INTERRUPT_FRAME_FT2(sp) |
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| 210 | FLREG ft3, RISCV_INTERRUPT_FRAME_FT3(sp) |
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| 211 | FLREG ft4, RISCV_INTERRUPT_FRAME_FT4(sp) |
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| 212 | FLREG ft5, RISCV_INTERRUPT_FRAME_FT5(sp) |
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| 213 | FLREG ft6, RISCV_INTERRUPT_FRAME_FT6(sp) |
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| 214 | FLREG ft7, RISCV_INTERRUPT_FRAME_FT7(sp) |
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| 215 | FLREG ft8, RISCV_INTERRUPT_FRAME_FT8(sp) |
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| 216 | FLREG ft9, RISCV_INTERRUPT_FRAME_FT9(sp) |
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| 217 | FLREG ft10, RISCV_INTERRUPT_FRAME_FT10(sp) |
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| 218 | FLREG ft11, RISCV_INTERRUPT_FRAME_FT11(sp) |
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| 219 | FLREG fa0, RISCV_INTERRUPT_FRAME_FA0(sp) |
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| 220 | FLREG fa1, RISCV_INTERRUPT_FRAME_FA1(sp) |
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| 221 | FLREG fa2, RISCV_INTERRUPT_FRAME_FA2(sp) |
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| 222 | FLREG fa3, RISCV_INTERRUPT_FRAME_FA3(sp) |
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| 223 | FLREG fa4, RISCV_INTERRUPT_FRAME_FA4(sp) |
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| 224 | FLREG fa5, RISCV_INTERRUPT_FRAME_FA5(sp) |
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| 225 | FLREG fa6, RISCV_INTERRUPT_FRAME_FA6(sp) |
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| 226 | FLREG fa7, RISCV_INTERRUPT_FRAME_FA7(sp) |
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| 227 | fscsr a0 |
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| 228 | #endif |
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[e43994d] | 229 | LREG a0, RISCV_INTERRUPT_FRAME_A0(sp) |
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| 230 | LREG a1, RISCV_INTERRUPT_FRAME_A1(sp) |
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| 231 | |
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| 232 | addi sp, sp, CPU_INTERRUPT_FRAME_SIZE |
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[52f4fb6] | 233 | |
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| 234 | mret |
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[8db3f0e] | 235 | |
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| 236 | .Lsynchronous_exception: |
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| 237 | |
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| 238 | SREG a0, RISCV_EXCEPTION_FRAME_MCAUSE(sp) |
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| 239 | addi a0, sp, CPU_INTERRUPT_FRAME_SIZE |
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| 240 | SREG a0, RISCV_EXCEPTION_FRAME_SP(sp) |
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| 241 | SREG gp, RISCV_EXCEPTION_FRAME_GP(sp) |
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| 242 | SREG tp, RISCV_EXCEPTION_FRAME_TP(sp) |
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| 243 | SREG s2, RISCV_EXCEPTION_FRAME_S2(sp) |
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| 244 | SREG s3, RISCV_EXCEPTION_FRAME_S3(sp) |
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| 245 | SREG s4, RISCV_EXCEPTION_FRAME_S4(sp) |
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| 246 | SREG s5, RISCV_EXCEPTION_FRAME_S5(sp) |
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| 247 | SREG s6, RISCV_EXCEPTION_FRAME_S6(sp) |
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| 248 | SREG s7, RISCV_EXCEPTION_FRAME_S7(sp) |
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| 249 | SREG s8, RISCV_EXCEPTION_FRAME_S8(sp) |
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| 250 | SREG s9, RISCV_EXCEPTION_FRAME_S9(sp) |
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| 251 | SREG s10, RISCV_EXCEPTION_FRAME_S10(sp) |
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| 252 | SREG s11, RISCV_EXCEPTION_FRAME_S11(sp) |
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| 253 | #if __riscv_flen > 0 |
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| 254 | FSREG fs0, RISCV_EXCEPTION_FRAME_FS0(sp) |
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| 255 | FSREG fs1, RISCV_EXCEPTION_FRAME_FS1(sp) |
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| 256 | FSREG fs2, RISCV_EXCEPTION_FRAME_FS2(sp) |
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| 257 | FSREG fs3, RISCV_EXCEPTION_FRAME_FS3(sp) |
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| 258 | FSREG fs4, RISCV_EXCEPTION_FRAME_FS4(sp) |
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| 259 | FSREG fs5, RISCV_EXCEPTION_FRAME_FS5(sp) |
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| 260 | FSREG fs6, RISCV_EXCEPTION_FRAME_FS6(sp) |
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| 261 | FSREG fs7, RISCV_EXCEPTION_FRAME_FS7(sp) |
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| 262 | FSREG fs8, RISCV_EXCEPTION_FRAME_FS8(sp) |
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| 263 | FSREG fs9, RISCV_EXCEPTION_FRAME_FS9(sp) |
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| 264 | FSREG fs10, RISCV_EXCEPTION_FRAME_FS10(sp) |
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| 265 | FSREG fs11, RISCV_EXCEPTION_FRAME_FS11(sp) |
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| 266 | #endif |
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| 267 | |
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| 268 | li a0, 9 |
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| 269 | mv a1, sp |
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| 270 | call _Terminate |
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