[660db8c8] | 1 | /* |
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[bcef89f2] | 2 | * Copyright (c) 2018 embedded brains GmbH & Co. KG |
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[660db8c8] | 3 | * Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk> |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * 1. Redistributions of source code must retain the above copyright |
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| 9 | * notice, this list of conditions and the following disclaimer. |
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| 10 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 11 | * notice, this list of conditions and the following disclaimer in the |
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| 12 | * documentation and/or other materials provided with the distribution. |
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| 13 | * |
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| 14 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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| 15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 16 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 17 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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| 18 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 19 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 20 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 21 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 22 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 23 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 24 | * SUCH DAMAGE. |
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| 25 | */ |
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| 26 | |
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| 27 | #ifdef HAVE_CONFIG_H |
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| 28 | #include "config.h" |
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| 29 | #endif |
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| 30 | |
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| 31 | #include <rtems/score/cpu.h> |
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| 32 | #include <rtems/bspIo.h> |
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| 33 | #include <inttypes.h> |
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| 34 | |
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[11ff3a9] | 35 | #if __riscv_xlen == 32 |
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[5694b0c] | 36 | #define PRINT_REG "0x%08" PRIxPTR |
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| 37 | #elif __riscv_xlen == 64 |
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| 38 | #define PRINT_REG "0x%016" PRIxPTR |
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[11ff3a9] | 39 | #endif |
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[5694b0c] | 40 | |
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| 41 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ) |
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| 42 | { |
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| 43 | printk("mstatus 0x%08" PRIxPTR "\n", frame->Interrupt_frame.mstatus); |
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| 44 | printk("mcause " PRINT_REG "\n", frame->mcause); |
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| 45 | printk("mepc " PRINT_REG "\n", frame->Interrupt_frame.mepc); |
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| 46 | printk("ra " PRINT_REG "\n", frame->Interrupt_frame.ra); |
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| 47 | printk("sp " PRINT_REG "\n", frame->sp); |
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| 48 | printk("gp " PRINT_REG "\n", frame->gp); |
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| 49 | printk("tp " PRINT_REG "\n", frame->tp); |
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| 50 | printk("t0 " PRINT_REG "\n", frame->Interrupt_frame.t0); |
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| 51 | printk("t1 " PRINT_REG "\n", frame->Interrupt_frame.t1); |
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| 52 | printk("t2 " PRINT_REG "\n", frame->Interrupt_frame.t2); |
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| 53 | printk("s0 " PRINT_REG "\n", frame->Interrupt_frame.s0); |
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| 54 | printk("s1 " PRINT_REG "\n", frame->Interrupt_frame.s1); |
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| 55 | printk("a0 " PRINT_REG "\n", frame->Interrupt_frame.a0); |
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| 56 | printk("a1 " PRINT_REG "\n", frame->Interrupt_frame.a1); |
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| 57 | printk("a2 " PRINT_REG "\n", frame->Interrupt_frame.a2); |
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| 58 | printk("a3 " PRINT_REG "\n", frame->Interrupt_frame.a3); |
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| 59 | printk("a4 " PRINT_REG "\n", frame->Interrupt_frame.a4); |
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| 60 | printk("a5 " PRINT_REG "\n", frame->Interrupt_frame.a5); |
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| 61 | printk("a6 " PRINT_REG "\n", frame->Interrupt_frame.a6); |
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| 62 | printk("a7 " PRINT_REG "\n", frame->Interrupt_frame.a7); |
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| 63 | printk("s2 " PRINT_REG "\n", frame->s2); |
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| 64 | printk("s3 " PRINT_REG "\n", frame->s3); |
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| 65 | printk("s4 " PRINT_REG "\n", frame->s4); |
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| 66 | printk("s5 " PRINT_REG "\n", frame->s5); |
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| 67 | printk("s6 " PRINT_REG "\n", frame->s6); |
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| 68 | printk("s7 " PRINT_REG "\n", frame->s7); |
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| 69 | printk("s8 " PRINT_REG "\n", frame->s8); |
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| 70 | printk("s9 " PRINT_REG "\n", frame->s9); |
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| 71 | printk("s10 " PRINT_REG "\n", frame->s10); |
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| 72 | printk("s11 " PRINT_REG "\n", frame->s11); |
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| 73 | printk("t3 " PRINT_REG "\n", frame->Interrupt_frame.t3); |
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| 74 | printk("t4 " PRINT_REG "\n", frame->Interrupt_frame.t4); |
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| 75 | printk("t5 " PRINT_REG "\n", frame->Interrupt_frame.t5); |
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| 76 | printk("t6 " PRINT_REG "\n", frame->Interrupt_frame.t6); |
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| 77 | #if __riscv_flen > 0 |
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| 78 | printk("fcsr 0x%08" PRIx32 "\n", frame->Interrupt_frame.fcsr); |
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| 79 | #endif /* __riscv_flen */ |
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[660db8c8] | 80 | } |
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