source: rtems/cpukit/score/cpu/riscv/riscv-exception-frame-print.c

Last change on this file was 5694b0c, checked in by Sebastian Huber <sebastian.huber@…>, on Jul 19, 2018 at 8:15:53 AM

riscv: New CPU_Exception_frame

Use the CPU_Interrupt_frame for the volatile context. Add non-volatile
registers and extra state on top of it.

Update #3433.

  • Property mode set to 100644
File size: 3.7 KB
Line 
1/*
2 * Copyright (c) 2018 embedded brains GmbH
3 * Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#ifdef HAVE_CONFIG_H
28#include "config.h"
29#endif
30
31#include <rtems/score/cpu.h>
32#include <rtems/bspIo.h>
33#include <inttypes.h>
34
35#if __riscv_xlen == 32
36#define PRINT_REG "0x%08" PRIxPTR
37#elif __riscv_xlen == 64
38#define PRINT_REG "0x%016" PRIxPTR
39#endif
40
41void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
42{
43  printk("mstatus 0x%08" PRIxPTR "\n", frame->Interrupt_frame.mstatus);
44  printk("mcause  " PRINT_REG "\n", frame->mcause);
45  printk("mepc    " PRINT_REG "\n", frame->Interrupt_frame.mepc);
46  printk("ra      " PRINT_REG "\n", frame->Interrupt_frame.ra);
47  printk("sp      " PRINT_REG "\n", frame->sp);
48  printk("gp      " PRINT_REG "\n", frame->gp);
49  printk("tp      " PRINT_REG "\n", frame->tp);
50  printk("t0      " PRINT_REG "\n", frame->Interrupt_frame.t0);
51  printk("t1      " PRINT_REG "\n", frame->Interrupt_frame.t1);
52  printk("t2      " PRINT_REG "\n", frame->Interrupt_frame.t2);
53  printk("s0      " PRINT_REG "\n", frame->Interrupt_frame.s0);
54  printk("s1      " PRINT_REG "\n", frame->Interrupt_frame.s1);
55  printk("a0      " PRINT_REG "\n", frame->Interrupt_frame.a0);
56  printk("a1      " PRINT_REG "\n", frame->Interrupt_frame.a1);
57  printk("a2      " PRINT_REG "\n", frame->Interrupt_frame.a2);
58  printk("a3      " PRINT_REG "\n", frame->Interrupt_frame.a3);
59  printk("a4      " PRINT_REG "\n", frame->Interrupt_frame.a4);
60  printk("a5      " PRINT_REG "\n", frame->Interrupt_frame.a5);
61  printk("a6      " PRINT_REG "\n", frame->Interrupt_frame.a6);
62  printk("a7      " PRINT_REG "\n", frame->Interrupt_frame.a7);
63  printk("s2      " PRINT_REG "\n", frame->s2);
64  printk("s3      " PRINT_REG "\n", frame->s3);
65  printk("s4      " PRINT_REG "\n", frame->s4);
66  printk("s5      " PRINT_REG "\n", frame->s5);
67  printk("s6      " PRINT_REG "\n", frame->s6);
68  printk("s7      " PRINT_REG "\n", frame->s7);
69  printk("s8      " PRINT_REG "\n", frame->s8);
70  printk("s9      " PRINT_REG "\n", frame->s9);
71  printk("s10     " PRINT_REG "\n", frame->s10);
72  printk("s11     " PRINT_REG "\n", frame->s11);
73  printk("t3      " PRINT_REG "\n", frame->Interrupt_frame.t3);
74  printk("t4      " PRINT_REG "\n", frame->Interrupt_frame.t4);
75  printk("t5      " PRINT_REG "\n", frame->Interrupt_frame.t5);
76  printk("t6      " PRINT_REG "\n", frame->Interrupt_frame.t6);
77#if __riscv_flen > 0
78  printk("fcsr    0x%08" PRIx32 "\n", frame->Interrupt_frame.fcsr);
79#endif /* __riscv_flen */
80}
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