source: rtems/cpukit/score/cpu/riscv/riscv-counter.S @ cfc9573

Last change on this file since cfc9573 was cfc9573, checked in by Sebastian Huber <sebastian.huber@…>, on Jul 27, 2018 at 12:47:17 PM

riscv: Rework CPU counter support

Update #3433.

  • Property mode set to 100644
File size: 1.8 KB
Line 
1/*
2 * Copyright (c) 2018 embedded brains GmbH
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#if __riscv_xlen == 32
27#define PTR_ALIGN 2
28#define PTR_SIZE 4
29#define PTR_VALUE .word
30#elif __riscv_xlen == 64
31#define PTR_ALIGN 3
32#define PTR_SIZE 8
33#define PTR_VALUE .dword
34#endif
35
36        .section        .sdata, "aw"
37        .align  PTR_ALIGN
38
39        .globl  _RISCV_Counter
40        .type   _RISCV_Counter, @object
41        .size   _RISCV_Counter, PTR_SIZE
42_RISCV_Counter:
43
44        .globl  _RISCV_Counter_mutable
45        .type   _RISCV_Counter_mutable, @object
46        .size   _RISCV_Counter_mutable, PTR_SIZE
47_RISCV_Counter_mutable:
48
49        PTR_VALUE       _RISCV_Counter_register
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