source: rtems/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S @ 8f035cb

5
Last change on this file since 8f035cb was 8f035cb, checked in by Sebastian Huber <sebastian.huber@…>, on 06/27/18 at 06:57:08

riscv: Implement _CPU_Context_volatile_clobber()

Update #3433.
  • Property mode set to 100644
File size: 1.8 KB
Line 
1/*
2 * Copyright (c) 2018 embedded brains GmbH
3 * Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#ifdef HAVE_CONFIG_H
28#include "config.h"
29#endif
30
31#include <rtems/asm.h>
32
33        .section        .text, "ax", @progbits
34        .align  2
35
36PUBLIC(_CPU_Context_volatile_clobber)
37SYM(_CPU_Context_volatile_clobber):
38
39        addi    a1, a0, 1
40        addi    a2, a0, 2
41        addi    a3, a0, 3
42        addi    a4, a0, 4
43        addi    a5, a0, 5
44        addi    a6, a0, 6
45        addi    a7, a0, 7
46        addi    t0, a0, 8
47        addi    t1, a0, 9
48        addi    t2, a0, 10
49        addi    t3, a0, 11
50        addi    t4, a0, 12
51        addi    t5, a0, 13
52        addi    t6, a0, 14
53
54        ret
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