source: rtems/cpukit/score/cpu/riscv/riscv-context-validate.S @ 11ff3a9

Last change on this file since 11ff3a9 was 11ff3a9, checked in by Hesham Almatary <heshamelmatary@…>, on Oct 27, 2017 at 4:18:40 AM

cpukit: RISC-V - make riscv32 code work for riscv64 - v2

  • Use #ifdefs for 32/64 bit code
  • Use unsigned long which is 32-bit on riscv32 and 64-bit on riscv64 (register size)
  • Move the code to a new shared riscv folder to be shared between riscv32 and riscv64
  • Rename RTEMS_CPU extracted from command line to shared riscv target s/riscv*/riscv

Update #3109

  • Property mode set to 100644
File size: 5.7 KB
Line 
1/*
2 * Copyrigh (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#ifdef HAVE_CONFIG_H
27#include "config.h"
28#endif
29
30#include <rtems/asm.h>
31#include <rtems/score/cpu.h>
32
33.section        .text
34
35
36PUBLIC(_CPU_Context_validate)
37SYM(_CPU_Context_validate):
38  /* RISC-V/RTEMS context has 36 registers of CPU_SIZEOF_POINTER size */
39  addi sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
40
41  SREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
42  /* Skip x2/sp */
43  SREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
44  SREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
45  SREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
46  SREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
47  SREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
48  SREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
49  SREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
50  SREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
51  SREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
52  SREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
53  SREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
54  SREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
55  SREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
56  SREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
57  SREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
58  SREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
59  SREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
60  SREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
61  SREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
62  SREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
63  SREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
64  SREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
65  SREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
66  SREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
67  SREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
68  SREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
69  SREG x29, (28 * CPU_SIZEOF_POINTER)(sp)
70  SREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
71  SREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
72
73  /* Fill */
74
75  /* t0 is used for temporary values */
76  mv t0, x0
77
78  /* x31 contains the stack pointer */
79  mv x31, sp
80
81  .macro fill_register reg
82  addi  t0, t0,  1
83  mv    \reg, t0
84  .endm
85
86  fill_register x1
87  fill_register x2
88  fill_register x3
89  fill_register x4
90  fill_register x5
91  fill_register x6
92  fill_register x7
93  fill_register x8
94  fill_register x9
95  fill_register x10
96  fill_register x11
97  fill_register x12
98  fill_register x13
99  fill_register x14
100  fill_register x15
101  fill_register x16
102  fill_register x17
103  fill_register x18
104  fill_register x19
105  fill_register x20
106  fill_register x21
107  fill_register x22
108  fill_register x23
109  fill_register x24
110  fill_register x25
111  fill_register x26
112  fill_register x27
113  fill_register x28
114  fill_register x29
115  fill_register x30
116  fill_register x31
117
118  /* Check */
119check:
120
121  .macro check_register reg
122  addi t0, t0, 1
123  bne \reg, t0, restore
124  .endm
125
126  bne   x31, sp, restore
127
128  mv t0, x0
129
130  check_register        x1
131  check_register        x2
132  check_register        x3
133  check_register        x4
134  check_register        x5
135  check_register        x6
136  check_register        x7
137  check_register        x8
138  check_register        x9
139  check_register        x10
140  check_register        x11
141  check_register        x12
142  check_register        x13
143  check_register        x14
144  check_register        x15
145  check_register        x16
146  check_register        x17
147  check_register        x18
148  check_register        x19
149  check_register        x20
150  check_register        x21
151  check_register        x22
152  check_register        x23
153  check_register        x24
154  check_register        x25
155  check_register        x26
156  check_register        x27
157  check_register        x28
158  check_register        x29
159  check_register        x30
160  check_register        x31
161
162  j check
163
164  /* Restore */
165restore:
166  LREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
167  /* Skip sp/x2 */
168  LREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
169  LREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
170  LREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
171  LREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
172  LREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
173  LREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
174  LREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
175  LREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
176  LREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
177  LREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
178  LREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
179  LREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
180  LREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
181  LREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
182  LREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
183  LREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
184  LREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
185  LREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
186  LREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
187  LREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
188  LREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
189  LREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
190  LREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
191  LREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
192  LREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
193  LREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
194  LREG x29, (29 * CPU_SIZEOF_POINTER)(sp)
195  LREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
196
197  LREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
198
199  addi sp, sp, 36 * CPU_SIZEOF_POINTER
200  ret
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