source: rtems/cpukit/score/cpu/riscv/riscv-context-switch.S @ e43994d

5
Last change on this file since e43994d was e43994d, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 27, 2018 at 8:05:50 AM

riscv: Optimize context switch and interrupts

Save/restore non-volatile registers in _CPU_Context_switch().

Save/restore volatile registers in _ISR_Handler().

Update #3433.

  • Property mode set to 100644
File size: 2.9 KB
Line 
1/*
2 * Copyright (c) 2018 embedded brains GmbH
3 *
4 * Copyright (c) 2015 University of York.
5 * Hesham ALmatary <hesham@alumni.york.ac.uk>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifdef HAVE_CONFIG_H
30#include "config.h"
31#endif
32
33#include <rtems/asm.h>
34#include <rtems/score/percpu.h>
35
36        .section        .text, "ax", @progbits
37        .align  2
38
39PUBLIC(_CPU_Context_switch)
40PUBLIC(_CPU_Context_restore)
41PUBLIC(_CPU_Context_restore_fp)
42PUBLIC(_CPU_Context_save_fp)
43
44SYM(_CPU_Context_switch):
45        GET_SELF_CPU_CONTROL    a2
46        lw      a3, PER_CPU_ISR_DISPATCH_DISABLE(a2)
47
48        SREG    ra, RISCV_CONTEXT_RA(a0)
49        SREG    sp, RISCV_CONTEXT_SP(a0)
50        SREG    s0, RISCV_CONTEXT_S0(a0)
51        SREG    s1, RISCV_CONTEXT_S1(a0)
52        SREG    s2, RISCV_CONTEXT_S2(a0)
53        SREG    s3, RISCV_CONTEXT_S3(a0)
54        SREG    s4, RISCV_CONTEXT_S4(a0)
55        SREG    s5, RISCV_CONTEXT_S5(a0)
56        SREG    s6, RISCV_CONTEXT_S6(a0)
57        SREG    s7, RISCV_CONTEXT_S7(a0)
58        SREG    s8, RISCV_CONTEXT_S8(a0)
59        SREG    s9, RISCV_CONTEXT_S9(a0)
60        SREG    s10, RISCV_CONTEXT_S10(a0)
61        SREG    s11, RISCV_CONTEXT_S11(a0)
62
63        sw      a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a0)
64
65.Lrestore:
66        lw      a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a1)
67
68        LREG    ra, RISCV_CONTEXT_RA(a1)
69        LREG    sp, RISCV_CONTEXT_SP(a1)
70        LREG    s0, RISCV_CONTEXT_S0(a1)
71        LREG    s1, RISCV_CONTEXT_S1(a1)
72        LREG    s2, RISCV_CONTEXT_S2(a1)
73        LREG    s3, RISCV_CONTEXT_S3(a1)
74        LREG    s4, RISCV_CONTEXT_S4(a1)
75        LREG    s5, RISCV_CONTEXT_S5(a1)
76        LREG    s6, RISCV_CONTEXT_S6(a1)
77        LREG    s7, RISCV_CONTEXT_S7(a1)
78        LREG    s8, RISCV_CONTEXT_S8(a1)
79        LREG    s9, RISCV_CONTEXT_S9(a1)
80        LREG    s10, RISCV_CONTEXT_S10(a1)
81        LREG    s11, RISCV_CONTEXT_S11(a1)
82
83        sw      a3, PER_CPU_ISR_DISPATCH_DISABLE(a2)
84
85        ret
86
87SYM(_CPU_Context_restore):
88        mv      a1, a0
89        GET_SELF_CPU_CONTROL    a2
90        j       .Lrestore
91
92        /* TODO no FP support for riscv32 yet */
93        SYM(_CPU_Context_restore_fp):
94        nop
95
96        SYM(_CPU_Context_save_fp):
97        nop
Note: See TracBrowser for help on using the repository browser.