source: rtems/cpukit/score/cpu/riscv/riscv-context-switch.S @ 11ff3a9

Last change on this file since 11ff3a9 was 11ff3a9, checked in by Hesham Almatary <heshamelmatary@…>, on Oct 27, 2017 at 4:18:40 AM

cpukit: RISC-V - make riscv32 code work for riscv64 - v2

  • Use #ifdefs for 32/64 bit code
  • Use unsigned long which is 32-bit on riscv32 and 64-bit on riscv64 (register size)
  • Move the code to a new shared riscv folder to be shared between riscv32 and riscv64
  • Rename RTEMS_CPU extracted from command line to shared riscv target s/riscv*/riscv

Update #3109

  • Property mode set to 100644
File size: 4.6 KB
Line 
1/*
2 * riscv32 CPU Dependent Source
3 *
4 * Copyright (c) 2015 University of York.
5 * Hesham ALmatary <hesham@alumni.york.ac.uk>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifdef HAVE_CONFIG_H
30#include "config.h"
31#endif
32
33#include <rtems/asm.h>
34#include <rtems/score/cpu.h>
35
36.section .text, "ax"
37.align 4
38
39PUBLIC(_CPU_Context_switch)
40PUBLIC(_CPU_Context_restore)
41PUBLIC(_CPU_Context_restore_fp)
42PUBLIC(_CPU_Context_save_fp)
43PUBLIC(restore)
44
45SYM(_CPU_Context_switch):
46  /* Disable interrupts and store all registers */
47  csrr t0, mstatus
48  SREG t0, (32 * CPU_SIZEOF_POINTER)(a0)
49
50  csrci mstatus, MSTATUS_MIE
51
52  SREG x1, (1 * CPU_SIZEOF_POINTER)(a0)
53  SREG x2, (2 * CPU_SIZEOF_POINTER)(a0)
54  SREG x3, (3 * CPU_SIZEOF_POINTER)(a0)
55  SREG x4, (4 * CPU_SIZEOF_POINTER)(a0)
56  SREG x5, (5 * CPU_SIZEOF_POINTER)(a0)
57  SREG x6, (6 * CPU_SIZEOF_POINTER)(a0)
58  SREG x7, (7 * CPU_SIZEOF_POINTER)(a0)
59  SREG x8, (8 * CPU_SIZEOF_POINTER)(a0)
60  SREG x9, (9 * CPU_SIZEOF_POINTER)(a0)
61  SREG x10, (10 * CPU_SIZEOF_POINTER)(a0)
62  SREG x11, (11 * CPU_SIZEOF_POINTER)(a0)
63  SREG x12, (12 * CPU_SIZEOF_POINTER)(a0)
64  SREG x13, (13 * CPU_SIZEOF_POINTER)(a0)
65  SREG x14, (14 * CPU_SIZEOF_POINTER)(a0)
66  SREG x15, (15 * CPU_SIZEOF_POINTER)(a0)
67  SREG x16, (16 * CPU_SIZEOF_POINTER)(a0)
68  SREG x17, (17 * CPU_SIZEOF_POINTER)(a0)
69  SREG x18, (18 * CPU_SIZEOF_POINTER)(a0)
70  SREG x19, (19 * CPU_SIZEOF_POINTER)(a0)
71  SREG x20, (20 * CPU_SIZEOF_POINTER)(a0)
72  SREG x21, (21 * CPU_SIZEOF_POINTER)(a0)
73  SREG x22, (22 * CPU_SIZEOF_POINTER)(a0)
74  SREG x23, (23 * CPU_SIZEOF_POINTER)(a0)
75  SREG x24, (24 * CPU_SIZEOF_POINTER)(a0)
76  SREG x25, (25 * CPU_SIZEOF_POINTER)(a0)
77  SREG x26, (26 * CPU_SIZEOF_POINTER)(a0)
78  SREG x27, (27 * CPU_SIZEOF_POINTER)(a0)
79  SREG x28, (28 * CPU_SIZEOF_POINTER)(a0)
80  SREG x29, (28 * CPU_SIZEOF_POINTER)(a0)
81  SREG x30, (30 * CPU_SIZEOF_POINTER)(a0)
82  SREG x31, (31 * CPU_SIZEOF_POINTER)(a0)
83
84  SYM(restore):
85
86  LREG x1, (1 * CPU_SIZEOF_POINTER)(a1)
87  LREG x2, (2 * CPU_SIZEOF_POINTER)(a1)
88  LREG x3, (3 * CPU_SIZEOF_POINTER)(a1)
89  LREG x4, (4 * CPU_SIZEOF_POINTER)(a1)
90  LREG x5, (5 * CPU_SIZEOF_POINTER)(a1)
91  LREG x6, (6 * CPU_SIZEOF_POINTER)(a1)
92  LREG x7, (7 * CPU_SIZEOF_POINTER)(a1)
93  LREG x8, (8 * CPU_SIZEOF_POINTER)(a1)
94  LREG x9, (9 * CPU_SIZEOF_POINTER)(a1)
95  LREG x10, (10 * CPU_SIZEOF_POINTER)(a1)
96  /* Skip a1/x11 */
97  LREG x12, (12 * CPU_SIZEOF_POINTER)(a1)
98  LREG x13, (13 * CPU_SIZEOF_POINTER)(a1)
99  LREG x14, (14 * CPU_SIZEOF_POINTER)(a1)
100  LREG x15, (15 * CPU_SIZEOF_POINTER)(a1)
101  LREG x16, (16 * CPU_SIZEOF_POINTER)(a1)
102  LREG x17, (17 * CPU_SIZEOF_POINTER)(a1)
103  LREG x18, (18 * CPU_SIZEOF_POINTER)(a1)
104  LREG x19, (19 * CPU_SIZEOF_POINTER)(a1)
105  LREG x20, (20 * CPU_SIZEOF_POINTER)(a1)
106  LREG x21, (21 * CPU_SIZEOF_POINTER)(a1)
107  LREG x22, (22 * CPU_SIZEOF_POINTER)(a1)
108  LREG x23, (23 * CPU_SIZEOF_POINTER)(a1)
109  LREG x24, (24 * CPU_SIZEOF_POINTER)(a1)
110  LREG x25, (25 * CPU_SIZEOF_POINTER)(a1)
111  LREG x26, (26 * CPU_SIZEOF_POINTER)(a1)
112  LREG x27, (27 * CPU_SIZEOF_POINTER)(a1)
113  LREG x28, (28 * CPU_SIZEOF_POINTER)(a1)
114  LREG x29, (29 * CPU_SIZEOF_POINTER)(a1)
115  LREG x30, (30 * CPU_SIZEOF_POINTER)(a1)
116
117  /* Load mstatus */
118  LREG x31, (32 * CPU_SIZEOF_POINTER)(a1)
119  csrw mstatus, x31
120
121  LREG x30, (30 * CPU_SIZEOF_POINTER)(a1)
122
123  LREG x11, (11 * CPU_SIZEOF_POINTER)(a1)
124
125  ret
126
127  SYM(_CPU_Context_restore):
128  mv     a1, a0
129  j      restore
130
131  /* TODO no FP support for riscv32 yet */
132  SYM(_CPU_Context_restore_fp):
133  nop
134
135  SYM(_CPU_Context_save_fp):
136  nop
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