1 | /* |
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2 | * Copyright (c) 2018 embedded brains GmbH & Co. KG |
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3 | * |
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4 | * Copyright (c) 2015 University of York. |
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5 | * Hesham ALmatary <hesham@alumni.york.ac.uk> |
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6 | * |
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7 | * Redistribution and use in source and binary forms, with or without |
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8 | * modification, are permitted provided that the following conditions |
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9 | * are met: |
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10 | * 1. Redistributions of source code must retain the above copyright |
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11 | * notice, this list of conditions and the following disclaimer. |
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12 | * 2. Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * |
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16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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26 | * SUCH DAMAGE. |
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27 | */ |
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28 | |
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29 | #ifdef HAVE_CONFIG_H |
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30 | #include "config.h" |
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31 | #endif |
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32 | |
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33 | #include <rtems/asm.h> |
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34 | #include <rtems/score/percpu.h> |
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35 | |
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36 | .section .text, "ax", @progbits |
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37 | .align 2 |
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38 | .option arch, +zicsr |
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39 | |
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40 | PUBLIC(_CPU_Context_switch) |
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41 | PUBLIC(_CPU_Context_switch_no_return) |
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42 | PUBLIC(_CPU_Context_restore) |
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43 | #ifdef RTEMS_SMP |
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44 | PUBLIC(_RISCV_Start_multitasking) |
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45 | #endif |
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46 | |
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47 | SYM(_CPU_Context_switch): |
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48 | SYM(_CPU_Context_switch_no_return): |
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49 | GET_SELF_CPU_CONTROL a2 |
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50 | lw a3, PER_CPU_ISR_DISPATCH_DISABLE(a2) |
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51 | |
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52 | #if __riscv_flen > 0 |
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53 | frcsr a4 |
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54 | #endif |
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55 | |
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56 | SREG ra, RISCV_CONTEXT_RA(a0) |
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57 | SREG sp, RISCV_CONTEXT_SP(a0) |
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58 | SREG s0, RISCV_CONTEXT_S0(a0) |
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59 | SREG s1, RISCV_CONTEXT_S1(a0) |
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60 | SREG s2, RISCV_CONTEXT_S2(a0) |
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61 | SREG s3, RISCV_CONTEXT_S3(a0) |
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62 | SREG s4, RISCV_CONTEXT_S4(a0) |
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63 | SREG s5, RISCV_CONTEXT_S5(a0) |
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64 | SREG s6, RISCV_CONTEXT_S6(a0) |
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65 | SREG s7, RISCV_CONTEXT_S7(a0) |
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66 | SREG s8, RISCV_CONTEXT_S8(a0) |
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67 | SREG s9, RISCV_CONTEXT_S9(a0) |
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68 | SREG s10, RISCV_CONTEXT_S10(a0) |
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69 | SREG s11, RISCV_CONTEXT_S11(a0) |
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70 | |
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71 | #if __riscv_flen > 0 |
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72 | sw a4, RISCV_CONTEXT_FCSR(a0) |
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73 | FSREG fs0, RISCV_CONTEXT_FS0(a0) |
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74 | FSREG fs1, RISCV_CONTEXT_FS1(a0) |
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75 | FSREG fs2, RISCV_CONTEXT_FS2(a0) |
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76 | FSREG fs3, RISCV_CONTEXT_FS3(a0) |
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77 | FSREG fs4, RISCV_CONTEXT_FS4(a0) |
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78 | FSREG fs5, RISCV_CONTEXT_FS5(a0) |
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79 | FSREG fs6, RISCV_CONTEXT_FS6(a0) |
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80 | FSREG fs7, RISCV_CONTEXT_FS7(a0) |
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81 | FSREG fs8, RISCV_CONTEXT_FS8(a0) |
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82 | FSREG fs9, RISCV_CONTEXT_FS9(a0) |
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83 | FSREG fs10, RISCV_CONTEXT_FS10(a0) |
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84 | FSREG fs11, RISCV_CONTEXT_FS11(a0) |
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85 | #endif |
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86 | |
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87 | sw a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a0) |
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88 | |
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89 | #ifdef RTEMS_SMP |
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90 | /* |
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91 | * The executing thread no longer executes on this processor. Switch |
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92 | * the stack to the temporary interrupt stack of this processor. Mark |
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93 | * the context of the executing thread as not executing. |
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94 | */ |
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95 | addi sp, a2, PER_CPU_INTERRUPT_FRAME_AREA + CPU_INTERRUPT_FRAME_SIZE |
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96 | amoswap.w.rl zero, zero, RISCV_CONTEXT_IS_EXECUTING(a0) |
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97 | |
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98 | .Ltry_update_is_executing: |
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99 | |
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100 | /* Try to update the is executing indicator of the heir context */ |
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101 | li a3, 1 |
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102 | amoswap.w.aq a3, a3, RISCV_CONTEXT_IS_EXECUTING(a1) |
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103 | bnez a3, .Lcheck_is_executing |
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104 | #endif |
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105 | |
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106 | .Lrestore: |
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107 | |
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108 | lw a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a1) |
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109 | |
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110 | LREG ra, RISCV_CONTEXT_RA(a1) |
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111 | LREG sp, RISCV_CONTEXT_SP(a1) |
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112 | LREG tp, RISCV_CONTEXT_TP(a1) |
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113 | LREG s0, RISCV_CONTEXT_S0(a1) |
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114 | LREG s1, RISCV_CONTEXT_S1(a1) |
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115 | LREG s2, RISCV_CONTEXT_S2(a1) |
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116 | LREG s3, RISCV_CONTEXT_S3(a1) |
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117 | LREG s4, RISCV_CONTEXT_S4(a1) |
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118 | LREG s5, RISCV_CONTEXT_S5(a1) |
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119 | LREG s6, RISCV_CONTEXT_S6(a1) |
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120 | LREG s7, RISCV_CONTEXT_S7(a1) |
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121 | LREG s8, RISCV_CONTEXT_S8(a1) |
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122 | LREG s9, RISCV_CONTEXT_S9(a1) |
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123 | LREG s10, RISCV_CONTEXT_S10(a1) |
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124 | LREG s11, RISCV_CONTEXT_S11(a1) |
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125 | |
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126 | #if __riscv_flen > 0 |
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127 | lw a4, RISCV_CONTEXT_FCSR(a1) |
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128 | FLREG fs0, RISCV_CONTEXT_FS0(a1) |
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129 | FLREG fs1, RISCV_CONTEXT_FS1(a1) |
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130 | FLREG fs2, RISCV_CONTEXT_FS2(a1) |
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131 | FLREG fs3, RISCV_CONTEXT_FS3(a1) |
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132 | FLREG fs4, RISCV_CONTEXT_FS4(a1) |
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133 | FLREG fs5, RISCV_CONTEXT_FS5(a1) |
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134 | FLREG fs6, RISCV_CONTEXT_FS6(a1) |
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135 | FLREG fs7, RISCV_CONTEXT_FS7(a1) |
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136 | FLREG fs8, RISCV_CONTEXT_FS8(a1) |
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137 | FLREG fs9, RISCV_CONTEXT_FS9(a1) |
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138 | FLREG fs10, RISCV_CONTEXT_FS10(a1) |
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139 | FLREG fs11, RISCV_CONTEXT_FS11(a1) |
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140 | fscsr a4 |
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141 | #endif |
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142 | |
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143 | sw a3, PER_CPU_ISR_DISPATCH_DISABLE(a2) |
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144 | |
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145 | CLEAR_RESERVATIONS a2 |
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146 | |
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147 | ret |
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148 | |
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149 | SYM(_CPU_Context_restore): |
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150 | mv a1, a0 |
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151 | GET_SELF_CPU_CONTROL a2 |
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152 | j .Lrestore |
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153 | |
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154 | #ifdef RTEMS_SMP |
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155 | .Lcheck_is_executing: |
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156 | |
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157 | /* Check the is executing indicator of the heir context */ |
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158 | lw a3, RISCV_CONTEXT_IS_EXECUTING(a1) |
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159 | beqz a3, .Ltry_update_is_executing |
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160 | |
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161 | /* We may have a new heir */ |
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162 | |
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163 | /* Read the executing and heir */ |
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164 | LREG a4, PER_CPU_OFFSET_EXECUTING(a2) |
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165 | LREG a5, PER_CPU_OFFSET_HEIR(a2) |
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166 | |
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167 | /* |
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168 | * Update the executing only if necessary to avoid cache line |
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169 | * monopolization. |
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170 | */ |
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171 | beq a4, a5, .Ltry_update_is_executing |
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172 | |
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173 | /* Calculate the heir context pointer */ |
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174 | sub a4, a1, a4 |
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175 | add a1, a5, a4 |
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176 | |
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177 | /* Update the executing */ |
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178 | sw a5, PER_CPU_OFFSET_EXECUTING(a2) |
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179 | |
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180 | j .Ltry_update_is_executing |
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181 | |
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182 | SYM(_RISCV_Start_multitasking): |
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183 | mv a1, a0 |
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184 | GET_SELF_CPU_CONTROL a2 |
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185 | |
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186 | /* Switch the stack to the temporary interrupt stack of this processor */ |
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187 | addi sp, a2, PER_CPU_INTERRUPT_FRAME_AREA + CPU_INTERRUPT_FRAME_SIZE |
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188 | |
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189 | /* Enable interrupts */ |
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190 | csrrs zero, mstatus, RISCV_MSTATUS_MIE |
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191 | |
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192 | j .Ltry_update_is_executing |
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193 | #endif |
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