source: rtems/cpukit/score/cpu/riscv/riscv-context-initialize.c @ e43994d

5
Last change on this file since e43994d was e43994d, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 27, 2018 at 8:05:50 AM

riscv: Optimize context switch and interrupts

Save/restore non-volatile registers in _CPU_Context_switch().

Save/restore volatile registers in _ISR_Handler().

Update #3433.

  • Property mode set to 100644
File size: 2.1 KB
RevLine 
[660db8c8]1/*
[04698eb]2 * Copyright (c) 2018 embedded brains GmbH
[660db8c8]3 *
4 * Copyright (c) 2015 University of York.
5 * Hesham Almatary <hesham@alumni.york.ac.uk>
6 *
7 * COPYRIGHT (c) 1989-2006.
8 * On-Line Applications Research Corporation (OAR).
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#ifdef HAVE_CONFIG_H
33#include "config.h"
34#endif
35
36#include <rtems/score/cpu.h>
[04698eb]37#include <rtems/score/address.h>
[660db8c8]38
39void _CPU_Context_Initialize(
40  Context_Control *context,
[a8188730]41  void            *stack_area_begin,
42  size_t           stack_area_size,
43  uint32_t         new_level,
44  void          ( *entry_point )( void ),
45  bool             is_fp,
46  void            *tls_area
[660db8c8]47)
48{
[04698eb]49  void *stack;
[660db8c8]50
[04698eb]51  stack = _Addresses_Add_offset( stack_area_begin, stack_area_size );
52  stack = _Addresses_Align_down( stack, CPU_STACK_ALIGNMENT );
[660db8c8]53
[e43994d]54  context->ra = (uintptr_t) entry_point;
55  context->sp = (uintptr_t) stack;
[a49a3c8e]56  context->isr_dispatch_disable = 0;
[660db8c8]57}
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