source: rtems/cpukit/score/cpu/riscv/riscv-context-initialize.c

Last change on this file was e07b51a7, checked in by Sebastian Huber <sebastian.huber@…>, on Jul 2, 2018 at 1:21:36 PM

riscv: Fix fcsr initialization

Update #3433.

  • Property mode set to 100644
File size: 2.5 KB
Line 
1/*
2 * Copyright (c) 2018 embedded brains GmbH
3 *
4 * Copyright (c) 2015 University of York.
5 * Hesham Almatary <hesham@alumni.york.ac.uk>
6 *
7 * COPYRIGHT (c) 1989-2006.
8 * On-Line Applications Research Corporation (OAR).
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#ifdef HAVE_CONFIG_H
33#include "config.h"
34#endif
35
36#include <rtems/score/cpuimpl.h>
37#include <rtems/score/address.h>
38#include <rtems/score/tls.h>
39
40void _CPU_Context_Initialize(
41  Context_Control *context,
42  void            *stack_area_begin,
43  size_t           stack_area_size,
44  uint32_t         new_level,
45  void          ( *entry_point )( void ),
46  bool             is_fp,
47  void            *tls_area
48)
49{
50  void *stack;
51
52  stack = _Addresses_Add_offset( stack_area_begin, stack_area_size );
53  stack = _Addresses_Align_down( stack, CPU_STACK_ALIGNMENT );
54
55  context->ra = (uintptr_t) entry_point;
56  context->sp = (uintptr_t) stack;
57  context->isr_dispatch_disable = 0;
58
59#if __riscv_flen > 0
60  /*
61   * According to C11 section 7.6 "Floating-point environment <fenv.h>" the
62   * floating-point environment shall be initialized to the current state of
63   * the creating thread.
64   */
65  context->fcsr = _RISCV_Read_FCSR();
66#endif
67
68  if ( tls_area != NULL ) {
69    void *tls_block;
70
71    tls_block = _TLS_TCB_before_TLS_block_initialize( tls_area );
72    context->tp = (uintptr_t) tls_block;
73  }
74}
Note: See TracBrowser for help on using the repository browser.