1 | /* Copyright (c) 2013, The Regents of the University of California (Regents). |
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2 | * All Rights Reserved. |
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3 | * |
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4 | * Redistribution and use in source and binary forms, with or without |
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5 | * modification, are permitted provided that the following conditions are met: |
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6 | * 1. Redistributions of source code must retain the above copyright |
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7 | * notice, this list of conditions and the following disclaimer. |
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8 | * 2. Redistributions in binary form must reproduce the above copyright |
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9 | * notice, this list of conditions and the following disclaimer in the |
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10 | * documentation and/or other materials provided with the distribution. |
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11 | * 3. Neither the name of the Regents nor the |
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12 | * names of its contributors may be used to endorse or promote products |
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13 | * derived from this software without specific prior written |
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14 | * permission. |
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15 | * |
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16 | * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, |
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17 | * INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST |
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18 | * PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF |
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19 | * REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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20 | * |
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21 | * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT |
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22 | * LIMITED TO,THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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23 | * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED |
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24 | * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE |
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25 | * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. |
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26 | */ |
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27 | |
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28 | /** |
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29 | * @file |
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30 | * |
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31 | * @brief RISCV utility |
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32 | */ |
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33 | /* |
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34 | * COPYRIGHT (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk> |
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35 | * |
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36 | * The license and distribution terms for this file may be |
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37 | * found in the file LICENSE in this distribution or at |
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38 | * http://www.rtems.org/license/LICENSE. |
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39 | */ |
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40 | |
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41 | /* This file is copied from riscv-tools/encoding.h with additions/modifications to work |
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42 | * with RTEMS. |
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43 | */ |
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44 | #ifndef _RTEMS_SCORE_RISCV_UTILITY_H |
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45 | #define _RTEMS_SCORE_RISCV_UTILITY_H |
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46 | |
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47 | #define MSTATUS_UIE 0x00000001 |
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48 | #define MSTATUS_SIE 0x00000002 |
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49 | #define MSTATUS_HIE 0x00000004 |
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50 | #define MSTATUS_MIE 0x00000008 |
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51 | #define MSTATUS_UPIE 0x00000010 |
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52 | #define MSTATUS_SPIE 0x00000020 |
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53 | #define MSTATUS_HPIE 0x00000040 |
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54 | #define MSTATUS_MPIE 0x00000080 |
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55 | #define MSTATUS_SPP 0x00000100 |
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56 | #define MSTATUS_HPP 0x00000600 |
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57 | #define MSTATUS_MPP 0x00001800 |
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58 | #define MSTATUS_FS 0x00006000 |
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59 | #define MSTATUS_XS 0x00018000 |
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60 | #define MSTATUS_MPRV 0x00020000 |
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61 | #define MSTATUS_SUM 0x00040000 |
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62 | #define MSTATUS_MXR 0x00080000 |
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63 | #define MSTATUS_TVM 0x00100000 |
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64 | #define MSTATUS_TW 0x00200000 |
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65 | #define MSTATUS_TSR 0x00400000 |
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66 | #define MSTATUS32_SD 0x80000000 |
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67 | #define MSTATUS64_SD 0x8000000000000000 |
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68 | |
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69 | #define SSTATUS_UIE 0x00000001 |
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70 | #define SSTATUS_SIE 0x00000002 |
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71 | #define SSTATUS_UPIE 0x00000010 |
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72 | #define SSTATUS_SPIE 0x00000020 |
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73 | #define SSTATUS_SPP 0x00000100 |
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74 | #define SSTATUS_FS 0x00006000 |
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75 | #define SSTATUS_XS 0x00018000 |
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76 | #define SSTATUS_SUM 0x00040000 |
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77 | #define SSTATUS_MXR 0x00080000 |
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78 | #define SSTATUS32_SD 0x80000000 |
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79 | #define SSTATUS64_SD 0x8000000000000000 |
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80 | |
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81 | #define DCSR_XDEBUGVER (3U<<30) |
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82 | #define DCSR_NDRESET (1<<29) |
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83 | #define DCSR_FULLRESET (1<<28) |
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84 | #define DCSR_EBREAKM (1<<15) |
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85 | #define DCSR_EBREAKH (1<<14) |
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86 | #define DCSR_EBREAKS (1<<13) |
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87 | #define DCSR_EBREAKU (1<<12) |
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88 | #define DCSR_STOPCYCLE (1<<10) |
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89 | #define DCSR_STOPTIME (1<<9) |
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90 | #define DCSR_CAUSE (7<<6) |
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91 | #define DCSR_DEBUGINT (1<<5) |
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92 | #define DCSR_HALT (1<<3) |
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93 | #define DCSR_STEP (1<<2) |
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94 | #define DCSR_PRV (3<<0) |
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95 | |
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96 | #define DCSR_CAUSE_NONE 0 |
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97 | #define DCSR_CAUSE_SWBP 1 |
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98 | #define DCSR_CAUSE_HWBP 2 |
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99 | #define DCSR_CAUSE_DEBUGINT 3 |
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100 | #define DCSR_CAUSE_STEP 4 |
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101 | #define DCSR_CAUSE_HALT 5 |
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102 | |
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103 | #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) |
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104 | #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) |
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105 | #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) |
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106 | |
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107 | #define MCONTROL_SELECT (1<<19) |
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108 | #define MCONTROL_TIMING (1<<18) |
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109 | #define MCONTROL_ACTION (0x3f<<12) |
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110 | #define MCONTROL_CHAIN (1<<11) |
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111 | #define MCONTROL_MATCH (0xf<<7) |
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112 | #define MCONTROL_M (1<<6) |
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113 | #define MCONTROL_H (1<<5) |
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114 | #define MCONTROL_S (1<<4) |
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115 | #define MCONTROL_U (1<<3) |
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116 | #define MCONTROL_EXECUTE (1<<2) |
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117 | #define MCONTROL_STORE (1<<1) |
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118 | #define MCONTROL_LOAD (1<<0) |
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119 | |
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120 | #define MCONTROL_TYPE_NONE 0 |
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121 | #define MCONTROL_TYPE_MATCH 2 |
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122 | |
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123 | #define MCONTROL_ACTION_DEBUG_EXCEPTION 0 |
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124 | #define MCONTROL_ACTION_DEBUG_MODE 1 |
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125 | #define MCONTROL_ACTION_TRACE_START 2 |
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126 | #define MCONTROL_ACTION_TRACE_STOP 3 |
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127 | #define MCONTROL_ACTION_TRACE_EMIT 4 |
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128 | |
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129 | #define MCONTROL_MATCH_EQUAL 0 |
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130 | #define MCONTROL_MATCH_NAPOT 1 |
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131 | #define MCONTROL_MATCH_GE 2 |
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132 | #define MCONTROL_MATCH_LT 3 |
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133 | #define MCONTROL_MATCH_MASK_LOW 4 |
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134 | #define MCONTROL_MATCH_MASK_HIGH 5 |
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135 | |
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136 | #define MIP_SSIP (1 << IRQ_S_SOFT) |
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137 | #define MIP_HSIP (1 << IRQ_H_SOFT) |
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138 | #define MIP_MSIP (1 << IRQ_M_SOFT) |
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139 | #define MIP_STIP (1 << IRQ_S_TIMER) |
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140 | #define MIP_HTIP (1 << IRQ_H_TIMER) |
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141 | #define MIP_MTIP (1 << IRQ_M_TIMER) |
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142 | #define MIP_SEIP (1 << IRQ_S_EXT) |
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143 | #define MIP_HEIP (1 << IRQ_H_EXT) |
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144 | #define MIP_MEIP (1 << IRQ_M_EXT) |
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145 | |
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146 | #define SIP_SSIP MIP_SSIP |
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147 | #define SIP_STIP MIP_STIP |
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148 | |
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149 | #define PRV_U 0 |
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150 | #define PRV_S 1 |
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151 | #define PRV_H 2 |
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152 | #define PRV_M 3 |
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153 | |
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154 | #define SPTBR32_MODE 0x80000000 |
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155 | #define SPTBR32_ASID 0x7FC00000 |
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156 | #define SPTBR32_PPN 0x003FFFFF |
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157 | #define SPTBR64_MODE 0xF000000000000000 |
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158 | #define SPTBR64_ASID 0x0FFFF00000000000 |
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159 | #define SPTBR64_PPN 0x00000FFFFFFFFFFF |
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160 | |
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161 | #define SPTBR_MODE_OFF 0 |
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162 | #define SPTBR_MODE_SV32 1 |
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163 | #define SPTBR_MODE_SV39 8 |
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164 | #define SPTBR_MODE_SV48 9 |
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165 | #define SPTBR_MODE_SV57 10 |
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166 | #define SPTBR_MODE_SV64 11 |
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167 | |
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168 | #define PMP_R 0x01 |
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169 | #define PMP_W 0x02 |
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170 | #define PMP_X 0x04 |
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171 | #define PMP_A 0x18 |
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172 | #define PMP_L 0x80 |
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173 | #define PMP_SHIFT 2 |
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174 | |
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175 | #define PMP_TOR 0x08 |
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176 | #define PMP_NA4 0x10 |
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177 | #define PMP_NAPOT 0x18 |
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178 | |
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179 | #define IRQ_S_SOFT 1 |
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180 | #define IRQ_H_SOFT 2 |
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181 | #define IRQ_M_SOFT 3 |
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182 | #define IRQ_S_TIMER 5 |
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183 | #define IRQ_H_TIMER 6 |
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184 | #define IRQ_M_TIMER 7 |
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185 | #define IRQ_S_EXT 9 |
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186 | #define IRQ_H_EXT 10 |
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187 | #define IRQ_M_EXT 11 |
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188 | #define IRQ_COP 12 |
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189 | #define IRQ_HOST 13 |
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190 | |
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191 | #define DEFAULT_RSTVEC 0x00001000 |
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192 | #define CLINT_BASE 0x02000000 |
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193 | #define CLINT_SIZE 0x000c0000 |
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194 | #define EXT_IO_BASE 0x40000000 |
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195 | #define DRAM_BASE 0x80000000 |
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196 | |
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197 | // page table entry (PTE) fields |
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198 | #define PTE_V 0x001 // Valid |
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199 | #define PTE_R 0x002 // Read |
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200 | #define PTE_W 0x004 // Write |
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201 | #define PTE_X 0x008 // Execute |
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202 | #define PTE_U 0x010 // User |
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203 | #define PTE_G 0x020 // Global |
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204 | #define PTE_A 0x040 // Accessed |
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205 | #define PTE_D 0x080 // Dirty |
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206 | #define PTE_SOFT 0x300 // Reserved for Software |
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207 | |
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208 | #define PTE_PPN_SHIFT 10 |
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209 | |
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210 | #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) |
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211 | |
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212 | #ifdef __riscv |
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213 | |
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214 | #if __riscv_xlen == 64 |
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215 | # define MSTATUS_SD MSTATUS64_SD |
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216 | # define SSTATUS_SD SSTATUS64_SD |
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217 | # define RISCV_PGLEVEL_BITS 9 |
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218 | # define SPTBR_MODE SPTBR64_MODE |
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219 | #else |
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220 | # define MSTATUS_SD MSTATUS32_SD |
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221 | # define SSTATUS_SD SSTATUS32_SD |
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222 | # define RISCV_PGLEVEL_BITS 10 |
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223 | # define SPTBR_MODE SPTBR32_MODE |
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224 | #endif |
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225 | #define RISCV_PGSHIFT 12 |
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226 | #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) |
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227 | |
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228 | #ifndef __ASSEMBLER__ |
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229 | |
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230 | /** |
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231 | * @brief Priv Mode registers definitions. |
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232 | * |
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233 | * @see RISC-V priv-spec 1.10. |
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234 | */ |
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235 | typedef enum { |
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236 | RISCV_USER_INTERRUPT = 0, |
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237 | RISCV_SUPERVISOR_SW_INTERRUPT = 1, |
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238 | RISCV_MACHINE_SW_INTERRUPT = 3, |
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239 | RISCV_USER_TIMER_INTERRUPT = 4, |
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240 | RISCV_SUPERVISOR_TIMER_INTERRUPT = 4, |
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241 | RISCV_MACHINE_TIMER_INTERRUPT = 7, |
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242 | RISCV_USER_EXTERNAL_INTERRUPT = 8, |
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243 | RISCV_SUPERVISOR_EXTERNAL_INTERRUPT = 9, |
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244 | RISCV_MACHINE_EXTERNAL_INTERRUPT = 11 |
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245 | } RISCV_Symbolic_interrupt_name; |
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246 | |
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247 | #ifdef __GNUC__ |
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248 | |
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249 | #define read_csr(reg) ({ unsigned long __tmp; \ |
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250 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ |
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251 | __tmp; }) |
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252 | |
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253 | #define write_csr(reg, val) ({ \ |
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254 | asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) |
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255 | |
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256 | #define swap_csr(reg, val) ({ unsigned long __tmp; \ |
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257 | asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ |
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258 | __tmp; }) |
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259 | |
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260 | #define set_csr(reg, bit) ({ unsigned long __tmp; \ |
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261 | asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ |
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262 | __tmp; }) |
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263 | |
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264 | #define clear_csr(reg, bit) ({ unsigned long __tmp; \ |
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265 | asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ |
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266 | __tmp; }) |
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267 | |
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268 | #define rdtime() read_csr(time) |
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269 | #define rdcycle() read_csr(cycle) |
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270 | #define rdinstret() read_csr(instret) |
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271 | |
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272 | #endif |
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273 | |
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274 | #endif |
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275 | |
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276 | #endif |
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277 | |
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278 | #endif |
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279 | /* Automatically generated by parse-opcodes. */ |
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280 | #ifndef RISCV_ENCODING_H |
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281 | #define RISCV_ENCODING_H |
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282 | #define MATCH_BEQ 0x63 |
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283 | #define MASK_BEQ 0x707f |
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284 | #define MATCH_BNE 0x1063 |
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285 | #define MASK_BNE 0x707f |
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286 | #define MATCH_BLT 0x4063 |
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287 | #define MASK_BLT 0x707f |
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288 | #define MATCH_BGE 0x5063 |
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289 | #define MASK_BGE 0x707f |
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290 | #define MATCH_BLTU 0x6063 |
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291 | #define MASK_BLTU 0x707f |
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292 | #define MATCH_BGEU 0x7063 |
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293 | #define MASK_BGEU 0x707f |
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294 | #define MATCH_JALR 0x67 |
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295 | #define MASK_JALR 0x707f |
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296 | #define MATCH_JAL 0x6f |
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297 | #define MASK_JAL 0x7f |
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298 | #define MATCH_LUI 0x37 |
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299 | #define MASK_LUI 0x7f |
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300 | #define MATCH_AUIPC 0x17 |
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301 | #define MASK_AUIPC 0x7f |
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302 | #define MATCH_ADDI 0x13 |
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303 | #define MASK_ADDI 0x707f |
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304 | #define MATCH_SLLI 0x1013 |
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305 | #define MASK_SLLI 0xfc00707f |
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306 | #define MATCH_SLTI 0x2013 |
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307 | #define MASK_SLTI 0x707f |
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308 | #define MATCH_SLTIU 0x3013 |
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309 | #define MASK_SLTIU 0x707f |
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310 | #define MATCH_XORI 0x4013 |
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311 | #define MASK_XORI 0x707f |
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312 | #define MATCH_SRLI 0x5013 |
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313 | #define MASK_SRLI 0xfc00707f |
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314 | #define MATCH_SRAI 0x40005013 |
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315 | #define MASK_SRAI 0xfc00707f |
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316 | #define MATCH_ORI 0x6013 |
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317 | #define MASK_ORI 0x707f |
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318 | #define MATCH_ANDI 0x7013 |
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319 | #define MASK_ANDI 0x707f |
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320 | #define MATCH_ADD 0x33 |
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321 | #define MASK_ADD 0xfe00707f |
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322 | #define MATCH_SUB 0x40000033 |
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323 | #define MASK_SUB 0xfe00707f |
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324 | #define MATCH_SLL 0x1033 |
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325 | #define MASK_SLL 0xfe00707f |
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326 | #define MATCH_SLT 0x2033 |
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327 | #define MASK_SLT 0xfe00707f |
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328 | #define MATCH_SLTU 0x3033 |
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329 | #define MASK_SLTU 0xfe00707f |
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330 | #define MATCH_XOR 0x4033 |
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331 | #define MASK_XOR 0xfe00707f |
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332 | #define MATCH_SRL 0x5033 |
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333 | #define MASK_SRL 0xfe00707f |
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334 | #define MATCH_SRA 0x40005033 |
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335 | #define MASK_SRA 0xfe00707f |
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336 | #define MATCH_OR 0x6033 |
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337 | #define MASK_OR 0xfe00707f |
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338 | #define MATCH_AND 0x7033 |
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339 | #define MASK_AND 0xfe00707f |
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340 | #define MATCH_ADDIW 0x1b |
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341 | #define MASK_ADDIW 0x707f |
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342 | #define MATCH_SLLIW 0x101b |
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343 | #define MASK_SLLIW 0xfe00707f |
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344 | #define MATCH_SRLIW 0x501b |
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345 | #define MASK_SRLIW 0xfe00707f |
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346 | #define MATCH_SRAIW 0x4000501b |
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347 | #define MASK_SRAIW 0xfe00707f |
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348 | #define MATCH_ADDW 0x3b |
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349 | #define MASK_ADDW 0xfe00707f |
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350 | #define MATCH_SUBW 0x4000003b |
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351 | #define MASK_SUBW 0xfe00707f |
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352 | #define MATCH_SLLW 0x103b |
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353 | #define MASK_SLLW 0xfe00707f |
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354 | #define MATCH_SRLW 0x503b |
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355 | #define MASK_SRLW 0xfe00707f |
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356 | #define MATCH_SRAW 0x4000503b |
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357 | #define MASK_SRAW 0xfe00707f |
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358 | #define MATCH_LB 0x3 |
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359 | #define MASK_LB 0x707f |
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360 | #define MATCH_LH 0x1003 |
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361 | #define MASK_LH 0x707f |
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362 | #define MATCH_LW 0x2003 |
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363 | #define MASK_LW 0x707f |
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364 | #define MATCH_LD 0x3003 |
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365 | #define MASK_LD 0x707f |
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366 | #define MATCH_LBU 0x4003 |
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367 | #define MASK_LBU 0x707f |
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368 | #define MATCH_LHU 0x5003 |
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369 | #define MASK_LHU 0x707f |
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370 | #define MATCH_LWU 0x6003 |
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371 | #define MASK_LWU 0x707f |
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372 | #define MATCH_SB 0x23 |
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373 | #define MASK_SB 0x707f |
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374 | #define MATCH_SH 0x1023 |
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375 | #define MASK_SH 0x707f |
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376 | #define MATCH_SW 0x2023 |
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377 | #define MASK_SW 0x707f |
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378 | #define MATCH_SD 0x3023 |
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379 | #define MASK_SD 0x707f |
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380 | #define MATCH_FENCE 0xf |
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381 | #define MASK_FENCE 0x707f |
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382 | #define MATCH_FENCE_I 0x100f |
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383 | #define MASK_FENCE_I 0x707f |
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384 | #define MATCH_MUL 0x2000033 |
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385 | #define MASK_MUL 0xfe00707f |
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386 | #define MATCH_MULH 0x2001033 |
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387 | #define MASK_MULH 0xfe00707f |
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388 | #define MATCH_MULHSU 0x2002033 |
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389 | #define MASK_MULHSU 0xfe00707f |
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390 | #define MATCH_MULHU 0x2003033 |
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391 | #define MASK_MULHU 0xfe00707f |
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392 | #define MATCH_DIV 0x2004033 |
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393 | #define MASK_DIV 0xfe00707f |
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394 | #define MATCH_DIVU 0x2005033 |
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395 | #define MASK_DIVU 0xfe00707f |
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396 | #define MATCH_REM 0x2006033 |
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397 | #define MASK_REM 0xfe00707f |
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398 | #define MATCH_REMU 0x2007033 |
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399 | #define MASK_REMU 0xfe00707f |
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400 | #define MATCH_MULW 0x200003b |
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401 | #define MASK_MULW 0xfe00707f |
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402 | #define MATCH_DIVW 0x200403b |
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403 | #define MASK_DIVW 0xfe00707f |
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404 | #define MATCH_DIVUW 0x200503b |
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405 | #define MASK_DIVUW 0xfe00707f |
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406 | #define MATCH_REMW 0x200603b |
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407 | #define MASK_REMW 0xfe00707f |
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408 | #define MATCH_REMUW 0x200703b |
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409 | #define MASK_REMUW 0xfe00707f |
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410 | #define MATCH_AMOADD_W 0x202f |
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411 | #define MASK_AMOADD_W 0xf800707f |
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412 | #define MATCH_AMOXOR_W 0x2000202f |
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413 | #define MASK_AMOXOR_W 0xf800707f |
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414 | #define MATCH_AMOOR_W 0x4000202f |
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415 | #define MASK_AMOOR_W 0xf800707f |
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416 | #define MATCH_AMOAND_W 0x6000202f |
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417 | #define MASK_AMOAND_W 0xf800707f |
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418 | #define MATCH_AMOMIN_W 0x8000202f |
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419 | #define MASK_AMOMIN_W 0xf800707f |
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420 | #define MATCH_AMOMAX_W 0xa000202f |
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421 | #define MASK_AMOMAX_W 0xf800707f |
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422 | #define MATCH_AMOMINU_W 0xc000202f |
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423 | #define MASK_AMOMINU_W 0xf800707f |
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424 | #define MATCH_AMOMAXU_W 0xe000202f |
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425 | #define MASK_AMOMAXU_W 0xf800707f |
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426 | #define MATCH_AMOSWAP_W 0x800202f |
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427 | #define MASK_AMOSWAP_W 0xf800707f |
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428 | #define MATCH_LR_W 0x1000202f |
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429 | #define MASK_LR_W 0xf9f0707f |
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430 | #define MATCH_SC_W 0x1800202f |
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431 | #define MASK_SC_W 0xf800707f |
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432 | #define MATCH_AMOADD_D 0x302f |
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433 | #define MASK_AMOADD_D 0xf800707f |
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434 | #define MATCH_AMOXOR_D 0x2000302f |
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435 | #define MASK_AMOXOR_D 0xf800707f |
---|
436 | #define MATCH_AMOOR_D 0x4000302f |
---|
437 | #define MASK_AMOOR_D 0xf800707f |
---|
438 | #define MATCH_AMOAND_D 0x6000302f |
---|
439 | #define MASK_AMOAND_D 0xf800707f |
---|
440 | #define MATCH_AMOMIN_D 0x8000302f |
---|
441 | #define MASK_AMOMIN_D 0xf800707f |
---|
442 | #define MATCH_AMOMAX_D 0xa000302f |
---|
443 | #define MASK_AMOMAX_D 0xf800707f |
---|
444 | #define MATCH_AMOMINU_D 0xc000302f |
---|
445 | #define MASK_AMOMINU_D 0xf800707f |
---|
446 | #define MATCH_AMOMAXU_D 0xe000302f |
---|
447 | #define MASK_AMOMAXU_D 0xf800707f |
---|
448 | #define MATCH_AMOSWAP_D 0x800302f |
---|
449 | #define MASK_AMOSWAP_D 0xf800707f |
---|
450 | #define MATCH_LR_D 0x1000302f |
---|
451 | #define MASK_LR_D 0xf9f0707f |
---|
452 | #define MATCH_SC_D 0x1800302f |
---|
453 | #define MASK_SC_D 0xf800707f |
---|
454 | #define MATCH_ECALL 0x73 |
---|
455 | #define MASK_ECALL 0xffffffff |
---|
456 | #define MATCH_EBREAK 0x100073 |
---|
457 | #define MASK_EBREAK 0xffffffff |
---|
458 | #define MATCH_URET 0x200073 |
---|
459 | #define MASK_URET 0xffffffff |
---|
460 | #define MATCH_SRET 0x10200073 |
---|
461 | #define MASK_SRET 0xffffffff |
---|
462 | #define MATCH_MRET 0x30200073 |
---|
463 | #define MASK_MRET 0xffffffff |
---|
464 | #define MATCH_DRET 0x7b200073 |
---|
465 | #define MASK_DRET 0xffffffff |
---|
466 | #define MATCH_SFENCE_VMA 0x12000073 |
---|
467 | #define MASK_SFENCE_VMA 0xfe007fff |
---|
468 | #define MATCH_WFI 0x10500073 |
---|
469 | #define MASK_WFI 0xffffffff |
---|
470 | #define MATCH_CSRRW 0x1073 |
---|
471 | #define MASK_CSRRW 0x707f |
---|
472 | #define MATCH_CSRRS 0x2073 |
---|
473 | #define MASK_CSRRS 0x707f |
---|
474 | #define MATCH_CSRRC 0x3073 |
---|
475 | #define MASK_CSRRC 0x707f |
---|
476 | #define MATCH_CSRRWI 0x5073 |
---|
477 | #define MASK_CSRRWI 0x707f |
---|
478 | #define MATCH_CSRRSI 0x6073 |
---|
479 | #define MASK_CSRRSI 0x707f |
---|
480 | #define MATCH_CSRRCI 0x7073 |
---|
481 | #define MASK_CSRRCI 0x707f |
---|
482 | #define MATCH_FADD_S 0x53 |
---|
483 | #define MASK_FADD_S 0xfe00007f |
---|
484 | #define MATCH_FSUB_S 0x8000053 |
---|
485 | #define MASK_FSUB_S 0xfe00007f |
---|
486 | #define MATCH_FMUL_S 0x10000053 |
---|
487 | #define MASK_FMUL_S 0xfe00007f |
---|
488 | #define MATCH_FDIV_S 0x18000053 |
---|
489 | #define MASK_FDIV_S 0xfe00007f |
---|
490 | #define MATCH_FSGNJ_S 0x20000053 |
---|
491 | #define MASK_FSGNJ_S 0xfe00707f |
---|
492 | #define MATCH_FSGNJN_S 0x20001053 |
---|
493 | #define MASK_FSGNJN_S 0xfe00707f |
---|
494 | #define MATCH_FSGNJX_S 0x20002053 |
---|
495 | #define MASK_FSGNJX_S 0xfe00707f |
---|
496 | #define MATCH_FMIN_S 0x28000053 |
---|
497 | #define MASK_FMIN_S 0xfe00707f |
---|
498 | #define MATCH_FMAX_S 0x28001053 |
---|
499 | #define MASK_FMAX_S 0xfe00707f |
---|
500 | #define MATCH_FSQRT_S 0x58000053 |
---|
501 | #define MASK_FSQRT_S 0xfff0007f |
---|
502 | #define MATCH_FADD_D 0x2000053 |
---|
503 | #define MASK_FADD_D 0xfe00007f |
---|
504 | #define MATCH_FSUB_D 0xa000053 |
---|
505 | #define MASK_FSUB_D 0xfe00007f |
---|
506 | #define MATCH_FMUL_D 0x12000053 |
---|
507 | #define MASK_FMUL_D 0xfe00007f |
---|
508 | #define MATCH_FDIV_D 0x1a000053 |
---|
509 | #define MASK_FDIV_D 0xfe00007f |
---|
510 | #define MATCH_FSGNJ_D 0x22000053 |
---|
511 | #define MASK_FSGNJ_D 0xfe00707f |
---|
512 | #define MATCH_FSGNJN_D 0x22001053 |
---|
513 | #define MASK_FSGNJN_D 0xfe00707f |
---|
514 | #define MATCH_FSGNJX_D 0x22002053 |
---|
515 | #define MASK_FSGNJX_D 0xfe00707f |
---|
516 | #define MATCH_FMIN_D 0x2a000053 |
---|
517 | #define MASK_FMIN_D 0xfe00707f |
---|
518 | #define MATCH_FMAX_D 0x2a001053 |
---|
519 | #define MASK_FMAX_D 0xfe00707f |
---|
520 | #define MATCH_FCVT_S_D 0x40100053 |
---|
521 | #define MASK_FCVT_S_D 0xfff0007f |
---|
522 | #define MATCH_FCVT_D_S 0x42000053 |
---|
523 | #define MASK_FCVT_D_S 0xfff0007f |
---|
524 | #define MATCH_FSQRT_D 0x5a000053 |
---|
525 | #define MASK_FSQRT_D 0xfff0007f |
---|
526 | #define MATCH_FADD_Q 0x6000053 |
---|
527 | #define MASK_FADD_Q 0xfe00007f |
---|
528 | #define MATCH_FSUB_Q 0xe000053 |
---|
529 | #define MASK_FSUB_Q 0xfe00007f |
---|
530 | #define MATCH_FMUL_Q 0x16000053 |
---|
531 | #define MASK_FMUL_Q 0xfe00007f |
---|
532 | #define MATCH_FDIV_Q 0x1e000053 |
---|
533 | #define MASK_FDIV_Q 0xfe00007f |
---|
534 | #define MATCH_FSGNJ_Q 0x26000053 |
---|
535 | #define MASK_FSGNJ_Q 0xfe00707f |
---|
536 | #define MATCH_FSGNJN_Q 0x26001053 |
---|
537 | #define MASK_FSGNJN_Q 0xfe00707f |
---|
538 | #define MATCH_FSGNJX_Q 0x26002053 |
---|
539 | #define MASK_FSGNJX_Q 0xfe00707f |
---|
540 | #define MATCH_FMIN_Q 0x2e000053 |
---|
541 | #define MASK_FMIN_Q 0xfe00707f |
---|
542 | #define MATCH_FMAX_Q 0x2e001053 |
---|
543 | #define MASK_FMAX_Q 0xfe00707f |
---|
544 | #define MATCH_FCVT_S_Q 0x40300053 |
---|
545 | #define MASK_FCVT_S_Q 0xfff0007f |
---|
546 | #define MATCH_FCVT_Q_S 0x46000053 |
---|
547 | #define MASK_FCVT_Q_S 0xfff0007f |
---|
548 | #define MATCH_FCVT_D_Q 0x42300053 |
---|
549 | #define MASK_FCVT_D_Q 0xfff0007f |
---|
550 | #define MATCH_FCVT_Q_D 0x46100053 |
---|
551 | #define MASK_FCVT_Q_D 0xfff0007f |
---|
552 | #define MATCH_FSQRT_Q 0x5e000053 |
---|
553 | #define MASK_FSQRT_Q 0xfff0007f |
---|
554 | #define MATCH_FLE_S 0xa0000053 |
---|
555 | #define MASK_FLE_S 0xfe00707f |
---|
556 | #define MATCH_FLT_S 0xa0001053 |
---|
557 | #define MASK_FLT_S 0xfe00707f |
---|
558 | #define MATCH_FEQ_S 0xa0002053 |
---|
559 | #define MASK_FEQ_S 0xfe00707f |
---|
560 | #define MATCH_FLE_D 0xa2000053 |
---|
561 | #define MASK_FLE_D 0xfe00707f |
---|
562 | #define MATCH_FLT_D 0xa2001053 |
---|
563 | #define MASK_FLT_D 0xfe00707f |
---|
564 | #define MATCH_FEQ_D 0xa2002053 |
---|
565 | #define MASK_FEQ_D 0xfe00707f |
---|
566 | #define MATCH_FLE_Q 0xa6000053 |
---|
567 | #define MASK_FLE_Q 0xfe00707f |
---|
568 | #define MATCH_FLT_Q 0xa6001053 |
---|
569 | #define MASK_FLT_Q 0xfe00707f |
---|
570 | #define MATCH_FEQ_Q 0xa6002053 |
---|
571 | #define MASK_FEQ_Q 0xfe00707f |
---|
572 | #define MATCH_FCVT_W_S 0xc0000053 |
---|
573 | #define MASK_FCVT_W_S 0xfff0007f |
---|
574 | #define MATCH_FCVT_WU_S 0xc0100053 |
---|
575 | #define MASK_FCVT_WU_S 0xfff0007f |
---|
576 | #define MATCH_FCVT_L_S 0xc0200053 |
---|
577 | #define MASK_FCVT_L_S 0xfff0007f |
---|
578 | #define MATCH_FCVT_LU_S 0xc0300053 |
---|
579 | #define MASK_FCVT_LU_S 0xfff0007f |
---|
580 | #define MATCH_FMV_X_W 0xe0000053 |
---|
581 | #define MASK_FMV_X_W 0xfff0707f |
---|
582 | #define MATCH_FCLASS_S 0xe0001053 |
---|
583 | #define MASK_FCLASS_S 0xfff0707f |
---|
584 | #define MATCH_FCVT_W_D 0xc2000053 |
---|
585 | #define MASK_FCVT_W_D 0xfff0007f |
---|
586 | #define MATCH_FCVT_WU_D 0xc2100053 |
---|
587 | #define MASK_FCVT_WU_D 0xfff0007f |
---|
588 | #define MATCH_FCVT_L_D 0xc2200053 |
---|
589 | #define MASK_FCVT_L_D 0xfff0007f |
---|
590 | #define MATCH_FCVT_LU_D 0xc2300053 |
---|
591 | #define MASK_FCVT_LU_D 0xfff0007f |
---|
592 | #define MATCH_FMV_X_D 0xe2000053 |
---|
593 | #define MASK_FMV_X_D 0xfff0707f |
---|
594 | #define MATCH_FCLASS_D 0xe2001053 |
---|
595 | #define MASK_FCLASS_D 0xfff0707f |
---|
596 | #define MATCH_FCVT_W_Q 0xc6000053 |
---|
597 | #define MASK_FCVT_W_Q 0xfff0007f |
---|
598 | #define MATCH_FCVT_WU_Q 0xc6100053 |
---|
599 | #define MASK_FCVT_WU_Q 0xfff0007f |
---|
600 | #define MATCH_FCVT_L_Q 0xc6200053 |
---|
601 | #define MASK_FCVT_L_Q 0xfff0007f |
---|
602 | #define MATCH_FCVT_LU_Q 0xc6300053 |
---|
603 | #define MASK_FCVT_LU_Q 0xfff0007f |
---|
604 | #define MATCH_FMV_X_Q 0xe6000053 |
---|
605 | #define MASK_FMV_X_Q 0xfff0707f |
---|
606 | #define MATCH_FCLASS_Q 0xe6001053 |
---|
607 | #define MASK_FCLASS_Q 0xfff0707f |
---|
608 | #define MATCH_FCVT_S_W 0xd0000053 |
---|
609 | #define MASK_FCVT_S_W 0xfff0007f |
---|
610 | #define MATCH_FCVT_S_WU 0xd0100053 |
---|
611 | #define MASK_FCVT_S_WU 0xfff0007f |
---|
612 | #define MATCH_FCVT_S_L 0xd0200053 |
---|
613 | #define MASK_FCVT_S_L 0xfff0007f |
---|
614 | #define MATCH_FCVT_S_LU 0xd0300053 |
---|
615 | #define MASK_FCVT_S_LU 0xfff0007f |
---|
616 | #define MATCH_FMV_W_X 0xf0000053 |
---|
617 | #define MASK_FMV_W_X 0xfff0707f |
---|
618 | #define MATCH_FCVT_D_W 0xd2000053 |
---|
619 | #define MASK_FCVT_D_W 0xfff0007f |
---|
620 | #define MATCH_FCVT_D_WU 0xd2100053 |
---|
621 | #define MASK_FCVT_D_WU 0xfff0007f |
---|
622 | #define MATCH_FCVT_D_L 0xd2200053 |
---|
623 | #define MASK_FCVT_D_L 0xfff0007f |
---|
624 | #define MATCH_FCVT_D_LU 0xd2300053 |
---|
625 | #define MASK_FCVT_D_LU 0xfff0007f |
---|
626 | #define MATCH_FMV_D_X 0xf2000053 |
---|
627 | #define MASK_FMV_D_X 0xfff0707f |
---|
628 | #define MATCH_FCVT_Q_W 0xd6000053 |
---|
629 | #define MASK_FCVT_Q_W 0xfff0007f |
---|
630 | #define MATCH_FCVT_Q_WU 0xd6100053 |
---|
631 | #define MASK_FCVT_Q_WU 0xfff0007f |
---|
632 | #define MATCH_FCVT_Q_L 0xd6200053 |
---|
633 | #define MASK_FCVT_Q_L 0xfff0007f |
---|
634 | #define MATCH_FCVT_Q_LU 0xd6300053 |
---|
635 | #define MASK_FCVT_Q_LU 0xfff0007f |
---|
636 | #define MATCH_FMV_Q_X 0xf6000053 |
---|
637 | #define MASK_FMV_Q_X 0xfff0707f |
---|
638 | #define MATCH_FLW 0x2007 |
---|
639 | #define MASK_FLW 0x707f |
---|
640 | #define MATCH_FLD 0x3007 |
---|
641 | #define MASK_FLD 0x707f |
---|
642 | #define MATCH_FLQ 0x4007 |
---|
643 | #define MASK_FLQ 0x707f |
---|
644 | #define MATCH_FSW 0x2027 |
---|
645 | #define MASK_FSW 0x707f |
---|
646 | #define MATCH_FSD 0x3027 |
---|
647 | #define MASK_FSD 0x707f |
---|
648 | #define MATCH_FSQ 0x4027 |
---|
649 | #define MASK_FSQ 0x707f |
---|
650 | #define MATCH_FMADD_S 0x43 |
---|
651 | #define MASK_FMADD_S 0x600007f |
---|
652 | #define MATCH_FMSUB_S 0x47 |
---|
653 | #define MASK_FMSUB_S 0x600007f |
---|
654 | #define MATCH_FNMSUB_S 0x4b |
---|
655 | #define MASK_FNMSUB_S 0x600007f |
---|
656 | #define MATCH_FNMADD_S 0x4f |
---|
657 | #define MASK_FNMADD_S 0x600007f |
---|
658 | #define MATCH_FMADD_D 0x2000043 |
---|
659 | #define MASK_FMADD_D 0x600007f |
---|
660 | #define MATCH_FMSUB_D 0x2000047 |
---|
661 | #define MASK_FMSUB_D 0x600007f |
---|
662 | #define MATCH_FNMSUB_D 0x200004b |
---|
663 | #define MASK_FNMSUB_D 0x600007f |
---|
664 | #define MATCH_FNMADD_D 0x200004f |
---|
665 | #define MASK_FNMADD_D 0x600007f |
---|
666 | #define MATCH_FMADD_Q 0x6000043 |
---|
667 | #define MASK_FMADD_Q 0x600007f |
---|
668 | #define MATCH_FMSUB_Q 0x6000047 |
---|
669 | #define MASK_FMSUB_Q 0x600007f |
---|
670 | #define MATCH_FNMSUB_Q 0x600004b |
---|
671 | #define MASK_FNMSUB_Q 0x600007f |
---|
672 | #define MATCH_FNMADD_Q 0x600004f |
---|
673 | #define MASK_FNMADD_Q 0x600007f |
---|
674 | #define MATCH_C_NOP 0x1 |
---|
675 | #define MASK_C_NOP 0xffff |
---|
676 | #define MATCH_C_ADDI16SP 0x6101 |
---|
677 | #define MASK_C_ADDI16SP 0xef83 |
---|
678 | #define MATCH_C_JR 0x8002 |
---|
679 | #define MASK_C_JR 0xf07f |
---|
680 | #define MATCH_C_JALR 0x9002 |
---|
681 | #define MASK_C_JALR 0xf07f |
---|
682 | #define MATCH_C_EBREAK 0x9002 |
---|
683 | #define MASK_C_EBREAK 0xffff |
---|
684 | #define MATCH_C_LD 0x6000 |
---|
685 | #define MASK_C_LD 0xe003 |
---|
686 | #define MATCH_C_SD 0xe000 |
---|
687 | #define MASK_C_SD 0xe003 |
---|
688 | #define MATCH_C_ADDIW 0x2001 |
---|
689 | #define MASK_C_ADDIW 0xe003 |
---|
690 | #define MATCH_C_LDSP 0x6002 |
---|
691 | #define MASK_C_LDSP 0xe003 |
---|
692 | #define MATCH_C_SDSP 0xe002 |
---|
693 | #define MASK_C_SDSP 0xe003 |
---|
694 | #define MATCH_C_ADDI4SPN 0x0 |
---|
695 | #define MASK_C_ADDI4SPN 0xe003 |
---|
696 | #define MATCH_C_FLD 0x2000 |
---|
697 | #define MASK_C_FLD 0xe003 |
---|
698 | #define MATCH_C_LW 0x4000 |
---|
699 | #define MASK_C_LW 0xe003 |
---|
700 | #define MATCH_C_FLW 0x6000 |
---|
701 | #define MASK_C_FLW 0xe003 |
---|
702 | #define MATCH_C_FSD 0xa000 |
---|
703 | #define MASK_C_FSD 0xe003 |
---|
704 | #define MATCH_C_SW 0xc000 |
---|
705 | #define MASK_C_SW 0xe003 |
---|
706 | #define MATCH_C_FSW 0xe000 |
---|
707 | #define MASK_C_FSW 0xe003 |
---|
708 | #define MATCH_C_ADDI 0x1 |
---|
709 | #define MASK_C_ADDI 0xe003 |
---|
710 | #define MATCH_C_JAL 0x2001 |
---|
711 | #define MASK_C_JAL 0xe003 |
---|
712 | #define MATCH_C_LI 0x4001 |
---|
713 | #define MASK_C_LI 0xe003 |
---|
714 | #define MATCH_C_LUI 0x6001 |
---|
715 | #define MASK_C_LUI 0xe003 |
---|
716 | #define MATCH_C_SRLI 0x8001 |
---|
717 | #define MASK_C_SRLI 0xec03 |
---|
718 | #define MATCH_C_SRAI 0x8401 |
---|
719 | #define MASK_C_SRAI 0xec03 |
---|
720 | #define MATCH_C_ANDI 0x8801 |
---|
721 | #define MASK_C_ANDI 0xec03 |
---|
722 | #define MATCH_C_SUB 0x8c01 |
---|
723 | #define MASK_C_SUB 0xfc63 |
---|
724 | #define MATCH_C_XOR 0x8c21 |
---|
725 | #define MASK_C_XOR 0xfc63 |
---|
726 | #define MATCH_C_OR 0x8c41 |
---|
727 | #define MASK_C_OR 0xfc63 |
---|
728 | #define MATCH_C_AND 0x8c61 |
---|
729 | #define MASK_C_AND 0xfc63 |
---|
730 | #define MATCH_C_SUBW 0x9c01 |
---|
731 | #define MASK_C_SUBW 0xfc63 |
---|
732 | #define MATCH_C_ADDW 0x9c21 |
---|
733 | #define MASK_C_ADDW 0xfc63 |
---|
734 | #define MATCH_C_J 0xa001 |
---|
735 | #define MASK_C_J 0xe003 |
---|
736 | #define MATCH_C_BEQZ 0xc001 |
---|
737 | #define MASK_C_BEQZ 0xe003 |
---|
738 | #define MATCH_C_BNEZ 0xe001 |
---|
739 | #define MASK_C_BNEZ 0xe003 |
---|
740 | #define MATCH_C_SLLI 0x2 |
---|
741 | #define MASK_C_SLLI 0xe003 |
---|
742 | #define MATCH_C_FLDSP 0x2002 |
---|
743 | #define MASK_C_FLDSP 0xe003 |
---|
744 | #define MATCH_C_LWSP 0x4002 |
---|
745 | #define MASK_C_LWSP 0xe003 |
---|
746 | #define MATCH_C_FLWSP 0x6002 |
---|
747 | #define MASK_C_FLWSP 0xe003 |
---|
748 | #define MATCH_C_MV 0x8002 |
---|
749 | #define MASK_C_MV 0xf003 |
---|
750 | #define MATCH_C_ADD 0x9002 |
---|
751 | #define MASK_C_ADD 0xf003 |
---|
752 | #define MATCH_C_FSDSP 0xa002 |
---|
753 | #define MASK_C_FSDSP 0xe003 |
---|
754 | #define MATCH_C_SWSP 0xc002 |
---|
755 | #define MASK_C_SWSP 0xe003 |
---|
756 | #define MATCH_C_FSWSP 0xe002 |
---|
757 | #define MASK_C_FSWSP 0xe003 |
---|
758 | #define MATCH_CUSTOM0 0xb |
---|
759 | #define MASK_CUSTOM0 0x707f |
---|
760 | #define MATCH_CUSTOM0_RS1 0x200b |
---|
761 | #define MASK_CUSTOM0_RS1 0x707f |
---|
762 | #define MATCH_CUSTOM0_RS1_RS2 0x300b |
---|
763 | #define MASK_CUSTOM0_RS1_RS2 0x707f |
---|
764 | #define MATCH_CUSTOM0_RD 0x400b |
---|
765 | #define MASK_CUSTOM0_RD 0x707f |
---|
766 | #define MATCH_CUSTOM0_RD_RS1 0x600b |
---|
767 | #define MASK_CUSTOM0_RD_RS1 0x707f |
---|
768 | #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b |
---|
769 | #define MASK_CUSTOM0_RD_RS1_RS2 0x707f |
---|
770 | #define MATCH_CUSTOM1 0x2b |
---|
771 | #define MASK_CUSTOM1 0x707f |
---|
772 | #define MATCH_CUSTOM1_RS1 0x202b |
---|
773 | #define MASK_CUSTOM1_RS1 0x707f |
---|
774 | #define MATCH_CUSTOM1_RS1_RS2 0x302b |
---|
775 | #define MASK_CUSTOM1_RS1_RS2 0x707f |
---|
776 | #define MATCH_CUSTOM1_RD 0x402b |
---|
777 | #define MASK_CUSTOM1_RD 0x707f |
---|
778 | #define MATCH_CUSTOM1_RD_RS1 0x602b |
---|
779 | #define MASK_CUSTOM1_RD_RS1 0x707f |
---|
780 | #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b |
---|
781 | #define MASK_CUSTOM1_RD_RS1_RS2 0x707f |
---|
782 | #define MATCH_CUSTOM2 0x5b |
---|
783 | #define MASK_CUSTOM2 0x707f |
---|
784 | #define MATCH_CUSTOM2_RS1 0x205b |
---|
785 | #define MASK_CUSTOM2_RS1 0x707f |
---|
786 | #define MATCH_CUSTOM2_RS1_RS2 0x305b |
---|
787 | #define MASK_CUSTOM2_RS1_RS2 0x707f |
---|
788 | #define MATCH_CUSTOM2_RD 0x405b |
---|
789 | #define MASK_CUSTOM2_RD 0x707f |
---|
790 | #define MATCH_CUSTOM2_RD_RS1 0x605b |
---|
791 | #define MASK_CUSTOM2_RD_RS1 0x707f |
---|
792 | #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b |
---|
793 | #define MASK_CUSTOM2_RD_RS1_RS2 0x707f |
---|
794 | #define MATCH_CUSTOM3 0x7b |
---|
795 | #define MASK_CUSTOM3 0x707f |
---|
796 | #define MATCH_CUSTOM3_RS1 0x207b |
---|
797 | #define MASK_CUSTOM3_RS1 0x707f |
---|
798 | #define MATCH_CUSTOM3_RS1_RS2 0x307b |
---|
799 | #define MASK_CUSTOM3_RS1_RS2 0x707f |
---|
800 | #define MATCH_CUSTOM3_RD 0x407b |
---|
801 | #define MASK_CUSTOM3_RD 0x707f |
---|
802 | #define MATCH_CUSTOM3_RD_RS1 0x607b |
---|
803 | #define MASK_CUSTOM3_RD_RS1 0x707f |
---|
804 | #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b |
---|
805 | #define MASK_CUSTOM3_RD_RS1_RS2 0x707f |
---|
806 | #define CSR_FFLAGS 0x1 |
---|
807 | #define CSR_FRM 0x2 |
---|
808 | #define CSR_FCSR 0x3 |
---|
809 | #define CSR_CYCLE 0xc00 |
---|
810 | #define CSR_TIME 0xc01 |
---|
811 | #define CSR_INSTRET 0xc02 |
---|
812 | #define CSR_HPMCOUNTER3 0xc03 |
---|
813 | #define CSR_HPMCOUNTER4 0xc04 |
---|
814 | #define CSR_HPMCOUNTER5 0xc05 |
---|
815 | #define CSR_HPMCOUNTER6 0xc06 |
---|
816 | #define CSR_HPMCOUNTER7 0xc07 |
---|
817 | #define CSR_HPMCOUNTER8 0xc08 |
---|
818 | #define CSR_HPMCOUNTER9 0xc09 |
---|
819 | #define CSR_HPMCOUNTER10 0xc0a |
---|
820 | #define CSR_HPMCOUNTER11 0xc0b |
---|
821 | #define CSR_HPMCOUNTER12 0xc0c |
---|
822 | #define CSR_HPMCOUNTER13 0xc0d |
---|
823 | #define CSR_HPMCOUNTER14 0xc0e |
---|
824 | #define CSR_HPMCOUNTER15 0xc0f |
---|
825 | #define CSR_HPMCOUNTER16 0xc10 |
---|
826 | #define CSR_HPMCOUNTER17 0xc11 |
---|
827 | #define CSR_HPMCOUNTER18 0xc12 |
---|
828 | #define CSR_HPMCOUNTER19 0xc13 |
---|
829 | #define CSR_HPMCOUNTER20 0xc14 |
---|
830 | #define CSR_HPMCOUNTER21 0xc15 |
---|
831 | #define CSR_HPMCOUNTER22 0xc16 |
---|
832 | #define CSR_HPMCOUNTER23 0xc17 |
---|
833 | #define CSR_HPMCOUNTER24 0xc18 |
---|
834 | #define CSR_HPMCOUNTER25 0xc19 |
---|
835 | #define CSR_HPMCOUNTER26 0xc1a |
---|
836 | #define CSR_HPMCOUNTER27 0xc1b |
---|
837 | #define CSR_HPMCOUNTER28 0xc1c |
---|
838 | #define CSR_HPMCOUNTER29 0xc1d |
---|
839 | #define CSR_HPMCOUNTER30 0xc1e |
---|
840 | #define CSR_HPMCOUNTER31 0xc1f |
---|
841 | #define CSR_SSTATUS 0x100 |
---|
842 | #define CSR_SIE 0x104 |
---|
843 | #define CSR_STVEC 0x105 |
---|
844 | #define CSR_SCOUNTEREN 0x106 |
---|
845 | #define CSR_SSCRATCH 0x140 |
---|
846 | #define CSR_SEPC 0x141 |
---|
847 | #define CSR_SCAUSE 0x142 |
---|
848 | #define CSR_SBADADDR 0x143 |
---|
849 | #define CSR_SIP 0x144 |
---|
850 | #define CSR_SPTBR 0x180 |
---|
851 | #define CSR_MSTATUS 0x300 |
---|
852 | #define CSR_MISA 0x301 |
---|
853 | #define CSR_MEDELEG 0x302 |
---|
854 | #define CSR_MIDELEG 0x303 |
---|
855 | #define CSR_MIE 0x304 |
---|
856 | #define CSR_MTVEC 0x305 |
---|
857 | #define CSR_MCOUNTEREN 0x306 |
---|
858 | #define CSR_MSCRATCH 0x340 |
---|
859 | #define CSR_MEPC 0x341 |
---|
860 | #define CSR_MCAUSE 0x342 |
---|
861 | #define CSR_MBADADDR 0x343 |
---|
862 | #define CSR_MIP 0x344 |
---|
863 | #define CSR_PMPCFG0 0x3a0 |
---|
864 | #define CSR_PMPCFG1 0x3a1 |
---|
865 | #define CSR_PMPCFG2 0x3a2 |
---|
866 | #define CSR_PMPCFG3 0x3a3 |
---|
867 | #define CSR_PMPADDR0 0x3b0 |
---|
868 | #define CSR_PMPADDR1 0x3b1 |
---|
869 | #define CSR_PMPADDR2 0x3b2 |
---|
870 | #define CSR_PMPADDR3 0x3b3 |
---|
871 | #define CSR_PMPADDR4 0x3b4 |
---|
872 | #define CSR_PMPADDR5 0x3b5 |
---|
873 | #define CSR_PMPADDR6 0x3b6 |
---|
874 | #define CSR_PMPADDR7 0x3b7 |
---|
875 | #define CSR_PMPADDR8 0x3b8 |
---|
876 | #define CSR_PMPADDR9 0x3b9 |
---|
877 | #define CSR_PMPADDR10 0x3ba |
---|
878 | #define CSR_PMPADDR11 0x3bb |
---|
879 | #define CSR_PMPADDR12 0x3bc |
---|
880 | #define CSR_PMPADDR13 0x3bd |
---|
881 | #define CSR_PMPADDR14 0x3be |
---|
882 | #define CSR_PMPADDR15 0x3bf |
---|
883 | #define CSR_TSELECT 0x7a0 |
---|
884 | #define CSR_TDATA1 0x7a1 |
---|
885 | #define CSR_TDATA2 0x7a2 |
---|
886 | #define CSR_TDATA3 0x7a3 |
---|
887 | #define CSR_DCSR 0x7b0 |
---|
888 | #define CSR_DPC 0x7b1 |
---|
889 | #define CSR_DSCRATCH 0x7b2 |
---|
890 | #define CSR_MCYCLE 0xb00 |
---|
891 | #define CSR_MINSTRET 0xb02 |
---|
892 | #define CSR_MHPMCOUNTER3 0xb03 |
---|
893 | #define CSR_MHPMCOUNTER4 0xb04 |
---|
894 | #define CSR_MHPMCOUNTER5 0xb05 |
---|
895 | #define CSR_MHPMCOUNTER6 0xb06 |
---|
896 | #define CSR_MHPMCOUNTER7 0xb07 |
---|
897 | #define CSR_MHPMCOUNTER8 0xb08 |
---|
898 | #define CSR_MHPMCOUNTER9 0xb09 |
---|
899 | #define CSR_MHPMCOUNTER10 0xb0a |
---|
900 | #define CSR_MHPMCOUNTER11 0xb0b |
---|
901 | #define CSR_MHPMCOUNTER12 0xb0c |
---|
902 | #define CSR_MHPMCOUNTER13 0xb0d |
---|
903 | #define CSR_MHPMCOUNTER14 0xb0e |
---|
904 | #define CSR_MHPMCOUNTER15 0xb0f |
---|
905 | #define CSR_MHPMCOUNTER16 0xb10 |
---|
906 | #define CSR_MHPMCOUNTER17 0xb11 |
---|
907 | #define CSR_MHPMCOUNTER18 0xb12 |
---|
908 | #define CSR_MHPMCOUNTER19 0xb13 |
---|
909 | #define CSR_MHPMCOUNTER20 0xb14 |
---|
910 | #define CSR_MHPMCOUNTER21 0xb15 |
---|
911 | #define CSR_MHPMCOUNTER22 0xb16 |
---|
912 | #define CSR_MHPMCOUNTER23 0xb17 |
---|
913 | #define CSR_MHPMCOUNTER24 0xb18 |
---|
914 | #define CSR_MHPMCOUNTER25 0xb19 |
---|
915 | #define CSR_MHPMCOUNTER26 0xb1a |
---|
916 | #define CSR_MHPMCOUNTER27 0xb1b |
---|
917 | #define CSR_MHPMCOUNTER28 0xb1c |
---|
918 | #define CSR_MHPMCOUNTER29 0xb1d |
---|
919 | #define CSR_MHPMCOUNTER30 0xb1e |
---|
920 | #define CSR_MHPMCOUNTER31 0xb1f |
---|
921 | #define CSR_MHPMEVENT3 0x323 |
---|
922 | #define CSR_MHPMEVENT4 0x324 |
---|
923 | #define CSR_MHPMEVENT5 0x325 |
---|
924 | #define CSR_MHPMEVENT6 0x326 |
---|
925 | #define CSR_MHPMEVENT7 0x327 |
---|
926 | #define CSR_MHPMEVENT8 0x328 |
---|
927 | #define CSR_MHPMEVENT9 0x329 |
---|
928 | #define CSR_MHPMEVENT10 0x32a |
---|
929 | #define CSR_MHPMEVENT11 0x32b |
---|
930 | #define CSR_MHPMEVENT12 0x32c |
---|
931 | #define CSR_MHPMEVENT13 0x32d |
---|
932 | #define CSR_MHPMEVENT14 0x32e |
---|
933 | #define CSR_MHPMEVENT15 0x32f |
---|
934 | #define CSR_MHPMEVENT16 0x330 |
---|
935 | #define CSR_MHPMEVENT17 0x331 |
---|
936 | #define CSR_MHPMEVENT18 0x332 |
---|
937 | #define CSR_MHPMEVENT19 0x333 |
---|
938 | #define CSR_MHPMEVENT20 0x334 |
---|
939 | #define CSR_MHPMEVENT21 0x335 |
---|
940 | #define CSR_MHPMEVENT22 0x336 |
---|
941 | #define CSR_MHPMEVENT23 0x337 |
---|
942 | #define CSR_MHPMEVENT24 0x338 |
---|
943 | #define CSR_MHPMEVENT25 0x339 |
---|
944 | #define CSR_MHPMEVENT26 0x33a |
---|
945 | #define CSR_MHPMEVENT27 0x33b |
---|
946 | #define CSR_MHPMEVENT28 0x33c |
---|
947 | #define CSR_MHPMEVENT29 0x33d |
---|
948 | #define CSR_MHPMEVENT30 0x33e |
---|
949 | #define CSR_MHPMEVENT31 0x33f |
---|
950 | #define CSR_MVENDORID 0xf11 |
---|
951 | #define CSR_MARCHID 0xf12 |
---|
952 | #define CSR_MIMPID 0xf13 |
---|
953 | #define CSR_MHARTID 0xf14 |
---|
954 | #define CSR_CYCLEH 0xc80 |
---|
955 | #define CSR_TIMEH 0xc81 |
---|
956 | #define CSR_INSTRETH 0xc82 |
---|
957 | #define CSR_HPMCOUNTER3H 0xc83 |
---|
958 | #define CSR_HPMCOUNTER4H 0xc84 |
---|
959 | #define CSR_HPMCOUNTER5H 0xc85 |
---|
960 | #define CSR_HPMCOUNTER6H 0xc86 |
---|
961 | #define CSR_HPMCOUNTER7H 0xc87 |
---|
962 | #define CSR_HPMCOUNTER8H 0xc88 |
---|
963 | #define CSR_HPMCOUNTER9H 0xc89 |
---|
964 | #define CSR_HPMCOUNTER10H 0xc8a |
---|
965 | #define CSR_HPMCOUNTER11H 0xc8b |
---|
966 | #define CSR_HPMCOUNTER12H 0xc8c |
---|
967 | #define CSR_HPMCOUNTER13H 0xc8d |
---|
968 | #define CSR_HPMCOUNTER14H 0xc8e |
---|
969 | #define CSR_HPMCOUNTER15H 0xc8f |
---|
970 | #define CSR_HPMCOUNTER16H 0xc90 |
---|
971 | #define CSR_HPMCOUNTER17H 0xc91 |
---|
972 | #define CSR_HPMCOUNTER18H 0xc92 |
---|
973 | #define CSR_HPMCOUNTER19H 0xc93 |
---|
974 | #define CSR_HPMCOUNTER20H 0xc94 |
---|
975 | #define CSR_HPMCOUNTER21H 0xc95 |
---|
976 | #define CSR_HPMCOUNTER22H 0xc96 |
---|
977 | #define CSR_HPMCOUNTER23H 0xc97 |
---|
978 | #define CSR_HPMCOUNTER24H 0xc98 |
---|
979 | #define CSR_HPMCOUNTER25H 0xc99 |
---|
980 | #define CSR_HPMCOUNTER26H 0xc9a |
---|
981 | #define CSR_HPMCOUNTER27H 0xc9b |
---|
982 | #define CSR_HPMCOUNTER28H 0xc9c |
---|
983 | #define CSR_HPMCOUNTER29H 0xc9d |
---|
984 | #define CSR_HPMCOUNTER30H 0xc9e |
---|
985 | #define CSR_HPMCOUNTER31H 0xc9f |
---|
986 | #define CSR_MCYCLEH 0xb80 |
---|
987 | #define CSR_MINSTRETH 0xb82 |
---|
988 | #define CSR_MHPMCOUNTER3H 0xb83 |
---|
989 | #define CSR_MHPMCOUNTER4H 0xb84 |
---|
990 | #define CSR_MHPMCOUNTER5H 0xb85 |
---|
991 | #define CSR_MHPMCOUNTER6H 0xb86 |
---|
992 | #define CSR_MHPMCOUNTER7H 0xb87 |
---|
993 | #define CSR_MHPMCOUNTER8H 0xb88 |
---|
994 | #define CSR_MHPMCOUNTER9H 0xb89 |
---|
995 | #define CSR_MHPMCOUNTER10H 0xb8a |
---|
996 | #define CSR_MHPMCOUNTER11H 0xb8b |
---|
997 | #define CSR_MHPMCOUNTER12H 0xb8c |
---|
998 | #define CSR_MHPMCOUNTER13H 0xb8d |
---|
999 | #define CSR_MHPMCOUNTER14H 0xb8e |
---|
1000 | #define CSR_MHPMCOUNTER15H 0xb8f |
---|
1001 | #define CSR_MHPMCOUNTER16H 0xb90 |
---|
1002 | #define CSR_MHPMCOUNTER17H 0xb91 |
---|
1003 | #define CSR_MHPMCOUNTER18H 0xb92 |
---|
1004 | #define CSR_MHPMCOUNTER19H 0xb93 |
---|
1005 | #define CSR_MHPMCOUNTER20H 0xb94 |
---|
1006 | #define CSR_MHPMCOUNTER21H 0xb95 |
---|
1007 | #define CSR_MHPMCOUNTER22H 0xb96 |
---|
1008 | #define CSR_MHPMCOUNTER23H 0xb97 |
---|
1009 | #define CSR_MHPMCOUNTER24H 0xb98 |
---|
1010 | #define CSR_MHPMCOUNTER25H 0xb99 |
---|
1011 | #define CSR_MHPMCOUNTER26H 0xb9a |
---|
1012 | #define CSR_MHPMCOUNTER27H 0xb9b |
---|
1013 | #define CSR_MHPMCOUNTER28H 0xb9c |
---|
1014 | #define CSR_MHPMCOUNTER29H 0xb9d |
---|
1015 | #define CSR_MHPMCOUNTER30H 0xb9e |
---|
1016 | #define CSR_MHPMCOUNTER31H 0xb9f |
---|
1017 | #define CAUSE_MISALIGNED_FETCH 0x0 |
---|
1018 | #define CAUSE_FETCH_ACCESS 0x1 |
---|
1019 | #define CAUSE_ILLEGAL_INSTRUCTION 0x2 |
---|
1020 | #define CAUSE_BREAKPOINT 0x3 |
---|
1021 | #define CAUSE_MISALIGNED_LOAD 0x4 |
---|
1022 | #define CAUSE_LOAD_ACCESS 0x5 |
---|
1023 | #define CAUSE_MISALIGNED_STORE 0x6 |
---|
1024 | #define CAUSE_STORE_ACCESS 0x7 |
---|
1025 | #define CAUSE_USER_ECALL 0x8 |
---|
1026 | #define CAUSE_SUPERVISOR_ECALL 0x9 |
---|
1027 | #define CAUSE_HYPERVISOR_ECALL 0xa |
---|
1028 | #define CAUSE_MACHINE_ECALL 0xb |
---|
1029 | #define CAUSE_FETCH_PAGE_FAULT 0xc |
---|
1030 | #define CAUSE_LOAD_PAGE_FAULT 0xd |
---|
1031 | #define CAUSE_STORE_PAGE_FAULT 0xf |
---|
1032 | #endif |
---|
1033 | #ifdef DECLARE_INSN |
---|
1034 | DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) |
---|
1035 | DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) |
---|
1036 | DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) |
---|
1037 | DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) |
---|
1038 | DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) |
---|
1039 | DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) |
---|
1040 | DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) |
---|
1041 | DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) |
---|
1042 | DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) |
---|
1043 | DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) |
---|
1044 | DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) |
---|
1045 | DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) |
---|
1046 | DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) |
---|
1047 | DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) |
---|
1048 | DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) |
---|
1049 | DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) |
---|
1050 | DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) |
---|
1051 | DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) |
---|
1052 | DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) |
---|
1053 | DECLARE_INSN(add, MATCH_ADD, MASK_ADD) |
---|
1054 | DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) |
---|
1055 | DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) |
---|
1056 | DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) |
---|
1057 | DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) |
---|
1058 | DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) |
---|
1059 | DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) |
---|
1060 | DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) |
---|
1061 | DECLARE_INSN( or , MATCH_OR, MASK_OR) |
---|
1062 | DECLARE_INSN( and , MATCH_AND, MASK_AND) |
---|
1063 | DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) |
---|
1064 | DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) |
---|
1065 | DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) |
---|
1066 | DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) |
---|
1067 | DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) |
---|
1068 | DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) |
---|
1069 | DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) |
---|
1070 | DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) |
---|
1071 | DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) |
---|
1072 | DECLARE_INSN(lb, MATCH_LB, MASK_LB) |
---|
1073 | DECLARE_INSN(lh, MATCH_LH, MASK_LH) |
---|
1074 | DECLARE_INSN(lw, MATCH_LW, MASK_LW) |
---|
1075 | DECLARE_INSN(ld, MATCH_LD, MASK_LD) |
---|
1076 | DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) |
---|
1077 | DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) |
---|
1078 | DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) |
---|
1079 | DECLARE_INSN(sb, MATCH_SB, MASK_SB) |
---|
1080 | DECLARE_INSN(sh, MATCH_SH, MASK_SH) |
---|
1081 | DECLARE_INSN(sw, MATCH_SW, MASK_SW) |
---|
1082 | DECLARE_INSN(sd, MATCH_SD, MASK_SD) |
---|
1083 | DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) |
---|
1084 | DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) |
---|
1085 | DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) |
---|
1086 | DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) |
---|
1087 | DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) |
---|
1088 | DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) |
---|
1089 | DECLARE_INSN(div, MATCH_DIV, MASK_DIV) |
---|
1090 | DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) |
---|
1091 | DECLARE_INSN(rem, MATCH_REM, MASK_REM) |
---|
1092 | DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) |
---|
1093 | DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) |
---|
1094 | DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) |
---|
1095 | DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) |
---|
1096 | DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) |
---|
1097 | DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) |
---|
1098 | DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) |
---|
1099 | DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) |
---|
1100 | DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) |
---|
1101 | DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) |
---|
1102 | DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) |
---|
1103 | DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) |
---|
1104 | DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) |
---|
1105 | DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) |
---|
1106 | DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) |
---|
1107 | DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) |
---|
1108 | DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) |
---|
1109 | DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) |
---|
1110 | DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) |
---|
1111 | DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) |
---|
1112 | DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) |
---|
1113 | DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) |
---|
1114 | DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) |
---|
1115 | DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) |
---|
1116 | DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) |
---|
1117 | DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) |
---|
1118 | DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) |
---|
1119 | DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) |
---|
1120 | DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) |
---|
1121 | DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) |
---|
1122 | DECLARE_INSN(uret, MATCH_URET, MASK_URET) |
---|
1123 | DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) |
---|
1124 | DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) |
---|
1125 | DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) |
---|
1126 | DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) |
---|
1127 | DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) |
---|
1128 | DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) |
---|
1129 | DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) |
---|
1130 | DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) |
---|
1131 | DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) |
---|
1132 | DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) |
---|
1133 | DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) |
---|
1134 | DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) |
---|
1135 | DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) |
---|
1136 | DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) |
---|
1137 | DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) |
---|
1138 | DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) |
---|
1139 | DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) |
---|
1140 | DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) |
---|
1141 | DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) |
---|
1142 | DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) |
---|
1143 | DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) |
---|
1144 | DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) |
---|
1145 | DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) |
---|
1146 | DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) |
---|
1147 | DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) |
---|
1148 | DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) |
---|
1149 | DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) |
---|
1150 | DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) |
---|
1151 | DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) |
---|
1152 | DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) |
---|
1153 | DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) |
---|
1154 | DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) |
---|
1155 | DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) |
---|
1156 | DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) |
---|
1157 | DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) |
---|
1158 | DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) |
---|
1159 | DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) |
---|
1160 | DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) |
---|
1161 | DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) |
---|
1162 | DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) |
---|
1163 | DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) |
---|
1164 | DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) |
---|
1165 | DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) |
---|
1166 | DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) |
---|
1167 | DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) |
---|
1168 | DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) |
---|
1169 | DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) |
---|
1170 | DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) |
---|
1171 | DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) |
---|
1172 | DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) |
---|
1173 | DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) |
---|
1174 | DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) |
---|
1175 | DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) |
---|
1176 | DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) |
---|
1177 | DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) |
---|
1178 | DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) |
---|
1179 | DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) |
---|
1180 | DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) |
---|
1181 | DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) |
---|
1182 | DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) |
---|
1183 | DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) |
---|
1184 | DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) |
---|
1185 | DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) |
---|
1186 | DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) |
---|
1187 | DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) |
---|
1188 | DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) |
---|
1189 | DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) |
---|
1190 | DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) |
---|
1191 | DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) |
---|
1192 | DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) |
---|
1193 | DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) |
---|
1194 | DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) |
---|
1195 | DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) |
---|
1196 | DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) |
---|
1197 | DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) |
---|
1198 | DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) |
---|
1199 | DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) |
---|
1200 | DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) |
---|
1201 | DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) |
---|
1202 | DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) |
---|
1203 | DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) |
---|
1204 | DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) |
---|
1205 | DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) |
---|
1206 | DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) |
---|
1207 | DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) |
---|
1208 | DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) |
---|
1209 | DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) |
---|
1210 | DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) |
---|
1211 | DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) |
---|
1212 | DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) |
---|
1213 | DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) |
---|
1214 | DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) |
---|
1215 | DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) |
---|
1216 | DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) |
---|
1217 | DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) |
---|
1218 | DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) |
---|
1219 | DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) |
---|
1220 | DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) |
---|
1221 | DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) |
---|
1222 | DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) |
---|
1223 | DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) |
---|
1224 | DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) |
---|
1225 | DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) |
---|
1226 | DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) |
---|
1227 | DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) |
---|
1228 | DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) |
---|
1229 | DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) |
---|
1230 | DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) |
---|
1231 | DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) |
---|
1232 | DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) |
---|
1233 | DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) |
---|
1234 | DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) |
---|
1235 | DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) |
---|
1236 | DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) |
---|
1237 | DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) |
---|
1238 | DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) |
---|
1239 | DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) |
---|
1240 | DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) |
---|
1241 | DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) |
---|
1242 | DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) |
---|
1243 | DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) |
---|
1244 | DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) |
---|
1245 | DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) |
---|
1246 | DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) |
---|
1247 | DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) |
---|
1248 | DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) |
---|
1249 | DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) |
---|
1250 | DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) |
---|
1251 | DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) |
---|
1252 | DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) |
---|
1253 | DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) |
---|
1254 | DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) |
---|
1255 | DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) |
---|
1256 | DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) |
---|
1257 | DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) |
---|
1258 | DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) |
---|
1259 | DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) |
---|
1260 | DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) |
---|
1261 | DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) |
---|
1262 | DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) |
---|
1263 | DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) |
---|
1264 | DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) |
---|
1265 | DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) |
---|
1266 | DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) |
---|
1267 | DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) |
---|
1268 | DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) |
---|
1269 | DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) |
---|
1270 | DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) |
---|
1271 | DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) |
---|
1272 | DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) |
---|
1273 | DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) |
---|
1274 | DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) |
---|
1275 | DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) |
---|
1276 | DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) |
---|
1277 | DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) |
---|
1278 | DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) |
---|
1279 | DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) |
---|
1280 | DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) |
---|
1281 | DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) |
---|
1282 | DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) |
---|
1283 | DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) |
---|
1284 | DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) |
---|
1285 | DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) |
---|
1286 | DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) |
---|
1287 | DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) |
---|
1288 | DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) |
---|
1289 | DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) |
---|
1290 | DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) |
---|
1291 | DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) |
---|
1292 | DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) |
---|
1293 | DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) |
---|
1294 | DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) |
---|
1295 | DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) |
---|
1296 | #endif |
---|
1297 | #ifdef DECLARE_CSR |
---|
1298 | DECLARE_CSR(fflags, CSR_FFLAGS) |
---|
1299 | DECLARE_CSR(frm, CSR_FRM) |
---|
1300 | DECLARE_CSR(fcsr, CSR_FCSR) |
---|
1301 | DECLARE_CSR(cycle, CSR_CYCLE) |
---|
1302 | DECLARE_CSR(time, CSR_TIME) |
---|
1303 | DECLARE_CSR(instret, CSR_INSTRET) |
---|
1304 | DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) |
---|
1305 | DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) |
---|
1306 | DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) |
---|
1307 | DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) |
---|
1308 | DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) |
---|
1309 | DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) |
---|
1310 | DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) |
---|
1311 | DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) |
---|
1312 | DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) |
---|
1313 | DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) |
---|
1314 | DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) |
---|
1315 | DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) |
---|
1316 | DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) |
---|
1317 | DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) |
---|
1318 | DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) |
---|
1319 | DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) |
---|
1320 | DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) |
---|
1321 | DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) |
---|
1322 | DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) |
---|
1323 | DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) |
---|
1324 | DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) |
---|
1325 | DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) |
---|
1326 | DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) |
---|
1327 | DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) |
---|
1328 | DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) |
---|
1329 | DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) |
---|
1330 | DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) |
---|
1331 | DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) |
---|
1332 | DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) |
---|
1333 | DECLARE_CSR(sstatus, CSR_SSTATUS) |
---|
1334 | DECLARE_CSR(sie, CSR_SIE) |
---|
1335 | DECLARE_CSR(stvec, CSR_STVEC) |
---|
1336 | DECLARE_CSR(scounteren, CSR_SCOUNTEREN) |
---|
1337 | DECLARE_CSR(sscratch, CSR_SSCRATCH) |
---|
1338 | DECLARE_CSR(sepc, CSR_SEPC) |
---|
1339 | DECLARE_CSR(scause, CSR_SCAUSE) |
---|
1340 | DECLARE_CSR(sbadaddr, CSR_SBADADDR) |
---|
1341 | DECLARE_CSR(sip, CSR_SIP) |
---|
1342 | DECLARE_CSR(sptbr, CSR_SPTBR) |
---|
1343 | DECLARE_CSR(mstatus, CSR_MSTATUS) |
---|
1344 | DECLARE_CSR(misa, CSR_MISA) |
---|
1345 | DECLARE_CSR(medeleg, CSR_MEDELEG) |
---|
1346 | DECLARE_CSR(mideleg, CSR_MIDELEG) |
---|
1347 | DECLARE_CSR(mie, CSR_MIE) |
---|
1348 | DECLARE_CSR(mtvec, CSR_MTVEC) |
---|
1349 | DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) |
---|
1350 | DECLARE_CSR(mscratch, CSR_MSCRATCH) |
---|
1351 | DECLARE_CSR(mepc, CSR_MEPC) |
---|
1352 | DECLARE_CSR(mcause, CSR_MCAUSE) |
---|
1353 | DECLARE_CSR(mbadaddr, CSR_MBADADDR) |
---|
1354 | DECLARE_CSR(mip, CSR_MIP) |
---|
1355 | DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) |
---|
1356 | DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) |
---|
1357 | DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) |
---|
1358 | DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) |
---|
1359 | DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) |
---|
1360 | DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) |
---|
1361 | DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) |
---|
1362 | DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) |
---|
1363 | DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) |
---|
1364 | DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) |
---|
1365 | DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) |
---|
1366 | DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) |
---|
1367 | DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) |
---|
1368 | DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) |
---|
1369 | DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) |
---|
1370 | DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) |
---|
1371 | DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) |
---|
1372 | DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) |
---|
1373 | DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) |
---|
1374 | DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) |
---|
1375 | DECLARE_CSR(tselect, CSR_TSELECT) |
---|
1376 | DECLARE_CSR(tdata1, CSR_TDATA1) |
---|
1377 | DECLARE_CSR(tdata2, CSR_TDATA2) |
---|
1378 | DECLARE_CSR(tdata3, CSR_TDATA3) |
---|
1379 | DECLARE_CSR(dcsr, CSR_DCSR) |
---|
1380 | DECLARE_CSR(dpc, CSR_DPC) |
---|
1381 | DECLARE_CSR(dscratch, CSR_DSCRATCH) |
---|
1382 | DECLARE_CSR(mcycle, CSR_MCYCLE) |
---|
1383 | DECLARE_CSR(minstret, CSR_MINSTRET) |
---|
1384 | DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) |
---|
1385 | DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) |
---|
1386 | DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) |
---|
1387 | DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) |
---|
1388 | DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) |
---|
1389 | DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) |
---|
1390 | DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) |
---|
1391 | DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) |
---|
1392 | DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) |
---|
1393 | DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) |
---|
1394 | DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) |
---|
1395 | DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) |
---|
1396 | DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) |
---|
1397 | DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) |
---|
1398 | DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) |
---|
1399 | DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) |
---|
1400 | DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) |
---|
1401 | DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) |
---|
1402 | DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) |
---|
1403 | DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) |
---|
1404 | DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) |
---|
1405 | DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) |
---|
1406 | DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) |
---|
1407 | DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) |
---|
1408 | DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) |
---|
1409 | DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) |
---|
1410 | DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) |
---|
1411 | DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) |
---|
1412 | DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) |
---|
1413 | DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) |
---|
1414 | DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) |
---|
1415 | DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) |
---|
1416 | DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) |
---|
1417 | DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) |
---|
1418 | DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) |
---|
1419 | DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) |
---|
1420 | DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) |
---|
1421 | DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) |
---|
1422 | DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) |
---|
1423 | DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) |
---|
1424 | DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) |
---|
1425 | DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) |
---|
1426 | DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) |
---|
1427 | DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) |
---|
1428 | DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) |
---|
1429 | DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) |
---|
1430 | DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) |
---|
1431 | DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) |
---|
1432 | DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) |
---|
1433 | DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) |
---|
1434 | DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) |
---|
1435 | DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) |
---|
1436 | DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) |
---|
1437 | DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) |
---|
1438 | DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) |
---|
1439 | DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) |
---|
1440 | DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) |
---|
1441 | DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) |
---|
1442 | DECLARE_CSR(mvendorid, CSR_MVENDORID) |
---|
1443 | DECLARE_CSR(marchid, CSR_MARCHID) |
---|
1444 | DECLARE_CSR(mimpid, CSR_MIMPID) |
---|
1445 | DECLARE_CSR(mhartid, CSR_MHARTID) |
---|
1446 | DECLARE_CSR(cycleh, CSR_CYCLEH) |
---|
1447 | DECLARE_CSR(timeh, CSR_TIMEH) |
---|
1448 | DECLARE_CSR(instreth, CSR_INSTRETH) |
---|
1449 | DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) |
---|
1450 | DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) |
---|
1451 | DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) |
---|
1452 | DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) |
---|
1453 | DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) |
---|
1454 | DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) |
---|
1455 | DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) |
---|
1456 | DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) |
---|
1457 | DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) |
---|
1458 | DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) |
---|
1459 | DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) |
---|
1460 | DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) |
---|
1461 | DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) |
---|
1462 | DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) |
---|
1463 | DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) |
---|
1464 | DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) |
---|
1465 | DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) |
---|
1466 | DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) |
---|
1467 | DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) |
---|
1468 | DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) |
---|
1469 | DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) |
---|
1470 | DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) |
---|
1471 | DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) |
---|
1472 | DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) |
---|
1473 | DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) |
---|
1474 | DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) |
---|
1475 | DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) |
---|
1476 | DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) |
---|
1477 | DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) |
---|
1478 | DECLARE_CSR(mcycleh, CSR_MCYCLEH) |
---|
1479 | DECLARE_CSR(minstreth, CSR_MINSTRETH) |
---|
1480 | DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) |
---|
1481 | DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) |
---|
1482 | DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) |
---|
1483 | DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) |
---|
1484 | DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) |
---|
1485 | DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) |
---|
1486 | DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) |
---|
1487 | DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) |
---|
1488 | DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) |
---|
1489 | DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) |
---|
1490 | DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) |
---|
1491 | DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) |
---|
1492 | DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) |
---|
1493 | DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) |
---|
1494 | DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) |
---|
1495 | DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) |
---|
1496 | DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) |
---|
1497 | DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) |
---|
1498 | DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) |
---|
1499 | DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) |
---|
1500 | DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) |
---|
1501 | DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) |
---|
1502 | DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) |
---|
1503 | DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) |
---|
1504 | DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) |
---|
1505 | DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) |
---|
1506 | DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) |
---|
1507 | DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) |
---|
1508 | DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) |
---|
1509 | #endif |
---|
1510 | #ifdef DECLARE_CAUSE |
---|
1511 | DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) |
---|
1512 | DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) |
---|
1513 | DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) |
---|
1514 | DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) |
---|
1515 | DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) |
---|
1516 | DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) |
---|
1517 | DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) |
---|
1518 | DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) |
---|
1519 | DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) |
---|
1520 | DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) |
---|
1521 | DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) |
---|
1522 | DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) |
---|
1523 | DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) |
---|
1524 | DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) |
---|
1525 | DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) |
---|
1526 | #endif |
---|