source: rtems/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @ e43994d

5
Last change on this file since e43994d was e43994d, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 27, 2018 at 8:05:50 AM

riscv: Optimize context switch and interrupts

Save/restore non-volatile registers in _CPU_Context_switch().

Save/restore volatile registers in _ISR_Handler().

Update #3433.

  • Property mode set to 100644
File size: 4.9 KB
Line 
1/**
2 * @file
3 *
4 * @brief CPU Port Implementation API
5 */
6
7/*
8 * Copyright (c) 2013, 2018 embedded brains GmbH
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#ifndef _RTEMS_SCORE_CPUIMPL_H
33#define _RTEMS_SCORE_CPUIMPL_H
34
35#include <rtems/score/cpu.h>
36
37#define CPU_PER_CPU_CONTROL_SIZE 0
38
39#ifdef RTEMS_SMP
40#define RISCV_CONTEXT_IS_EXECUTING 0
41#endif
42
43#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 4
44
45#if __riscv_xlen == 32
46
47#define RISCV_CONTEXT_RA 8
48#define RISCV_CONTEXT_SP 12
49#define RISCV_CONTEXT_TP 16
50#define RISCV_CONTEXT_S0 20
51#define RISCV_CONTEXT_S1 24
52#define RISCV_CONTEXT_S2 28
53#define RISCV_CONTEXT_S3 32
54#define RISCV_CONTEXT_S4 36
55#define RISCV_CONTEXT_S5 40
56#define RISCV_CONTEXT_S6 44
57#define RISCV_CONTEXT_S7 48
58#define RISCV_CONTEXT_S8 52
59#define RISCV_CONTEXT_S9 56
60#define RISCV_CONTEXT_S10 60
61#define RISCV_CONTEXT_S11 64
62
63#define RISCV_INTERRUPT_FRAME_MSTATUS 0
64#define RISCV_INTERRUPT_FRAME_MEPC 4
65#define RISCV_INTERRUPT_FRAME_A2 8
66#define RISCV_INTERRUPT_FRAME_S0 12
67#define RISCV_INTERRUPT_FRAME_S1 16
68#define RISCV_INTERRUPT_FRAME_RA 20
69#define RISCV_INTERRUPT_FRAME_A3 24
70#define RISCV_INTERRUPT_FRAME_A4 28
71#define RISCV_INTERRUPT_FRAME_A5 32
72#define RISCV_INTERRUPT_FRAME_A6 36
73#define RISCV_INTERRUPT_FRAME_A7 40
74#define RISCV_INTERRUPT_FRAME_T0 44
75#define RISCV_INTERRUPT_FRAME_T1 48
76#define RISCV_INTERRUPT_FRAME_T2 52
77#define RISCV_INTERRUPT_FRAME_T3 56
78#define RISCV_INTERRUPT_FRAME_T4 60
79#define RISCV_INTERRUPT_FRAME_T5 64
80#define RISCV_INTERRUPT_FRAME_T6 68
81#define RISCV_INTERRUPT_FRAME_A0 72
82#define RISCV_INTERRUPT_FRAME_A1 76
83
84#define CPU_INTERRUPT_FRAME_SIZE 80
85
86#elif __riscv_xlen == 64
87
88#define RISCV_CONTEXT_RA 8
89#define RISCV_CONTEXT_SP 16
90#define RISCV_CONTEXT_TP 24
91#define RISCV_CONTEXT_S0 32
92#define RISCV_CONTEXT_S1 40
93#define RISCV_CONTEXT_S2 48
94#define RISCV_CONTEXT_S3 56
95#define RISCV_CONTEXT_S4 64
96#define RISCV_CONTEXT_S5 72
97#define RISCV_CONTEXT_S6 80
98#define RISCV_CONTEXT_S7 88
99#define RISCV_CONTEXT_S8 96
100#define RISCV_CONTEXT_S9 104
101#define RISCV_CONTEXT_S10 112
102#define RISCV_CONTEXT_S11 120
103
104#define RISCV_INTERRUPT_FRAME_MSTATUS 0
105#define RISCV_INTERRUPT_FRAME_MEPC 8
106#define RISCV_INTERRUPT_FRAME_A2 16
107#define RISCV_INTERRUPT_FRAME_S0 24
108#define RISCV_INTERRUPT_FRAME_S1 32
109#define RISCV_INTERRUPT_FRAME_RA 40
110#define RISCV_INTERRUPT_FRAME_A3 48
111#define RISCV_INTERRUPT_FRAME_A4 56
112#define RISCV_INTERRUPT_FRAME_A5 64
113#define RISCV_INTERRUPT_FRAME_A6 72
114#define RISCV_INTERRUPT_FRAME_A7 80
115#define RISCV_INTERRUPT_FRAME_T0 88
116#define RISCV_INTERRUPT_FRAME_T1 96
117#define RISCV_INTERRUPT_FRAME_T2 104
118#define RISCV_INTERRUPT_FRAME_T3 112
119#define RISCV_INTERRUPT_FRAME_T4 120
120#define RISCV_INTERRUPT_FRAME_T5 128
121#define RISCV_INTERRUPT_FRAME_T6 136
122#define RISCV_INTERRUPT_FRAME_A0 144
123#define RISCV_INTERRUPT_FRAME_A1 152
124
125#define CPU_INTERRUPT_FRAME_SIZE 160
126
127#endif /* __riscv_xlen */
128
129#ifndef ASM
130
131#ifdef __cplusplus
132extern "C" {
133#endif
134
135typedef struct {
136  uintptr_t mstatus;
137  uintptr_t mepc;
138  uintptr_t a2;
139  uintptr_t s0;
140  uintptr_t s1;
141  uintptr_t ra;
142  uintptr_t a3;
143  uintptr_t a4;
144  uintptr_t a5;
145  uintptr_t a6;
146  uintptr_t a7;
147  uintptr_t t0;
148  uintptr_t t1;
149  uintptr_t t2;
150  uintptr_t t3;
151  uintptr_t t4;
152  uintptr_t t5;
153  uintptr_t t6;
154  uintptr_t a0;
155  uintptr_t a1;
156} RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame;
157
158#ifdef RTEMS_SMP
159
160static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void )
161{
162  struct Per_CPU_Control *cpu_self;
163
164  __asm__ volatile ( "csrr %0, mscratch" : "=r" ( cpu_self ) );
165
166  return cpu_self;
167}
168
169#define _CPU_Get_current_per_CPU_control() _RISCV_Get_current_per_CPU_control()
170
171#endif /* RTEMS_SMP */
172
173#ifdef __cplusplus
174}
175#endif
176
177#endif /* ASM */
178
179#endif /* _RTEMS_SCORE_CPUIMPL_H */
Note: See TracBrowser for help on using the repository browser.