source: rtems/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @ b74353e

5
Last change on this file since b74353e was b74353e, checked in by Sebastian Huber <sebastian.huber@…>, on 07/20/18 at 06:06:46

score: Add _CPU_Instruction_no_operation()

This helps to reduce the use of architecture-specific defines throughout
the code base.

  • Property mode set to 100644
File size: 9.0 KB
Line 
1/**
2 * @file
3 *
4 * @brief CPU Port Implementation API
5 */
6
7/*
8 * Copyright (c) 2013, 2018 embedded brains GmbH
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#ifndef _RTEMS_SCORE_CPUIMPL_H
33#define _RTEMS_SCORE_CPUIMPL_H
34
35#include <rtems/score/cpu.h>
36
37#ifdef __riscv_atomic
38#define CPU_PER_CPU_CONTROL_SIZE 16
39#else
40#define CPU_PER_CPU_CONTROL_SIZE 0
41#endif
42
43#ifdef RTEMS_SMP
44#define RISCV_CONTEXT_IS_EXECUTING 0
45#endif
46
47#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 4
48
49#if __riscv_xlen == 32
50
51#define RISCV_CONTEXT_RA 8
52#define RISCV_CONTEXT_SP 12
53#define RISCV_CONTEXT_TP 16
54#define RISCV_CONTEXT_S0 20
55#define RISCV_CONTEXT_S1 24
56#define RISCV_CONTEXT_S2 28
57#define RISCV_CONTEXT_S3 32
58#define RISCV_CONTEXT_S4 36
59#define RISCV_CONTEXT_S5 40
60#define RISCV_CONTEXT_S6 44
61#define RISCV_CONTEXT_S7 48
62#define RISCV_CONTEXT_S8 52
63#define RISCV_CONTEXT_S9 56
64#define RISCV_CONTEXT_S10 60
65#define RISCV_CONTEXT_S11 64
66
67#define RISCV_INTERRUPT_FRAME_MSTATUS 0
68#define RISCV_INTERRUPT_FRAME_MEPC 4
69#define RISCV_INTERRUPT_FRAME_A2 8
70#define RISCV_INTERRUPT_FRAME_S0 12
71#define RISCV_INTERRUPT_FRAME_S1 16
72#define RISCV_INTERRUPT_FRAME_RA 20
73#define RISCV_INTERRUPT_FRAME_A3 24
74#define RISCV_INTERRUPT_FRAME_A4 28
75#define RISCV_INTERRUPT_FRAME_A5 32
76#define RISCV_INTERRUPT_FRAME_A6 36
77#define RISCV_INTERRUPT_FRAME_A7 40
78#define RISCV_INTERRUPT_FRAME_T0 44
79#define RISCV_INTERRUPT_FRAME_T1 48
80#define RISCV_INTERRUPT_FRAME_T2 52
81#define RISCV_INTERRUPT_FRAME_T3 56
82#define RISCV_INTERRUPT_FRAME_T4 60
83#define RISCV_INTERRUPT_FRAME_T5 64
84#define RISCV_INTERRUPT_FRAME_T6 68
85
86#if __riscv_flen == 0
87
88#define RISCV_INTERRUPT_FRAME_A0 72
89#define RISCV_INTERRUPT_FRAME_A1 76
90
91#define CPU_INTERRUPT_FRAME_SIZE 80
92
93#elif __riscv_flen == 32
94
95#define RISCV_CONTEXT_FCSR 68
96
97#define RISCV_CONTEXT_F( x ) (72 + 4 * (x))
98
99#define RISCV_INTERRUPT_FRAME_FCSR 72
100
101#define RISCV_INTERRUPT_FRAME_F( x ) (76 + 4 * (x))
102
103#define RISCV_INTERRUPT_FRAME_A0 156
104#define RISCV_INTERRUPT_FRAME_A1 160
105
106#define CPU_INTERRUPT_FRAME_SIZE 176
107
108#elif __riscv_flen == 64
109
110#define RISCV_CONTEXT_FCSR 68
111
112#define RISCV_CONTEXT_F( x ) (72 + 8 * (x))
113
114#define RISCV_INTERRUPT_FRAME_FCSR 72
115
116#define RISCV_INTERRUPT_FRAME_F( x ) (80 + 8 * (x))
117
118#define RISCV_INTERRUPT_FRAME_A0 240
119#define RISCV_INTERRUPT_FRAME_A1 244
120
121#define CPU_INTERRUPT_FRAME_SIZE 256
122
123#endif /* __riscv_flen */
124
125#elif __riscv_xlen == 64
126
127#define RISCV_CONTEXT_RA 8
128#define RISCV_CONTEXT_SP 16
129#define RISCV_CONTEXT_TP 24
130#define RISCV_CONTEXT_S0 32
131#define RISCV_CONTEXT_S1 40
132#define RISCV_CONTEXT_S2 48
133#define RISCV_CONTEXT_S3 56
134#define RISCV_CONTEXT_S4 64
135#define RISCV_CONTEXT_S5 72
136#define RISCV_CONTEXT_S6 80
137#define RISCV_CONTEXT_S7 88
138#define RISCV_CONTEXT_S8 96
139#define RISCV_CONTEXT_S9 104
140#define RISCV_CONTEXT_S10 112
141#define RISCV_CONTEXT_S11 120
142
143#define RISCV_INTERRUPT_FRAME_MSTATUS 0
144#define RISCV_INTERRUPT_FRAME_MEPC 8
145#define RISCV_INTERRUPT_FRAME_A2 16
146#define RISCV_INTERRUPT_FRAME_S0 24
147#define RISCV_INTERRUPT_FRAME_S1 32
148#define RISCV_INTERRUPT_FRAME_RA 40
149#define RISCV_INTERRUPT_FRAME_A3 48
150#define RISCV_INTERRUPT_FRAME_A4 56
151#define RISCV_INTERRUPT_FRAME_A5 64
152#define RISCV_INTERRUPT_FRAME_A6 72
153#define RISCV_INTERRUPT_FRAME_A7 80
154#define RISCV_INTERRUPT_FRAME_T0 88
155#define RISCV_INTERRUPT_FRAME_T1 96
156#define RISCV_INTERRUPT_FRAME_T2 104
157#define RISCV_INTERRUPT_FRAME_T3 112
158#define RISCV_INTERRUPT_FRAME_T4 120
159#define RISCV_INTERRUPT_FRAME_T5 128
160#define RISCV_INTERRUPT_FRAME_T6 136
161
162#if __riscv_flen == 0
163
164#define RISCV_INTERRUPT_FRAME_A0 144
165#define RISCV_INTERRUPT_FRAME_A1 152
166
167#define CPU_INTERRUPT_FRAME_SIZE 160
168
169#elif __riscv_flen == 32
170
171#define RISCV_CONTEXT_FCSR 128
172
173#define RISCV_CONTEXT_F( x ) (132 + 4 * (x))
174
175#define RISCV_INTERRUPT_FRAME_FCSR 144
176
177#define RISCV_INTERRUPT_FRAME_F( x ) (148 + 4 * (x))
178
179#define RISCV_INTERRUPT_FRAME_A0 232
180#define RISCV_INTERRUPT_FRAME_A1 240
181
182#define CPU_INTERRUPT_FRAME_SIZE 256
183
184#elif __riscv_flen == 64
185
186#define RISCV_CONTEXT_FCSR 128
187
188#define RISCV_CONTEXT_F( x ) (136 + 8 * (x))
189
190#define RISCV_INTERRUPT_FRAME_FCSR 144
191
192#define RISCV_INTERRUPT_FRAME_F( x ) (152 + 8 * (x))
193
194#define RISCV_INTERRUPT_FRAME_A0 312
195#define RISCV_INTERRUPT_FRAME_A1 320
196
197#define CPU_INTERRUPT_FRAME_SIZE 336
198
199#endif /* __riscv_flen */
200
201#endif /* __riscv_xlen */
202
203#if __riscv_flen > 0
204
205#define RISCV_CONTEXT_FS0 RISCV_CONTEXT_F( 0 )
206#define RISCV_CONTEXT_FS1 RISCV_CONTEXT_F( 1 )
207#define RISCV_CONTEXT_FS2 RISCV_CONTEXT_F( 2 )
208#define RISCV_CONTEXT_FS3 RISCV_CONTEXT_F( 3 )
209#define RISCV_CONTEXT_FS4 RISCV_CONTEXT_F( 4 )
210#define RISCV_CONTEXT_FS5 RISCV_CONTEXT_F( 5 )
211#define RISCV_CONTEXT_FS6 RISCV_CONTEXT_F( 6 )
212#define RISCV_CONTEXT_FS7 RISCV_CONTEXT_F( 7 )
213#define RISCV_CONTEXT_FS8 RISCV_CONTEXT_F( 8 )
214#define RISCV_CONTEXT_FS9 RISCV_CONTEXT_F( 9 )
215#define RISCV_CONTEXT_FS10 RISCV_CONTEXT_F( 10 )
216#define RISCV_CONTEXT_FS11 RISCV_CONTEXT_F( 11 )
217
218#define RISCV_INTERRUPT_FRAME_FT0 RISCV_INTERRUPT_FRAME_F( 0 )
219#define RISCV_INTERRUPT_FRAME_FT1 RISCV_INTERRUPT_FRAME_F( 1 )
220#define RISCV_INTERRUPT_FRAME_FT2 RISCV_INTERRUPT_FRAME_F( 2 )
221#define RISCV_INTERRUPT_FRAME_FT3 RISCV_INTERRUPT_FRAME_F( 3 )
222#define RISCV_INTERRUPT_FRAME_FT4 RISCV_INTERRUPT_FRAME_F( 4 )
223#define RISCV_INTERRUPT_FRAME_FT5 RISCV_INTERRUPT_FRAME_F( 5 )
224#define RISCV_INTERRUPT_FRAME_FT6 RISCV_INTERRUPT_FRAME_F( 6 )
225#define RISCV_INTERRUPT_FRAME_FT7 RISCV_INTERRUPT_FRAME_F( 7 )
226#define RISCV_INTERRUPT_FRAME_FT8 RISCV_INTERRUPT_FRAME_F( 8 )
227#define RISCV_INTERRUPT_FRAME_FT9 RISCV_INTERRUPT_FRAME_F( 9 )
228#define RISCV_INTERRUPT_FRAME_FT10 RISCV_INTERRUPT_FRAME_F( 10 )
229#define RISCV_INTERRUPT_FRAME_FT11 RISCV_INTERRUPT_FRAME_F( 11 )
230#define RISCV_INTERRUPT_FRAME_FA0 RISCV_INTERRUPT_FRAME_F( 12 )
231#define RISCV_INTERRUPT_FRAME_FA1 RISCV_INTERRUPT_FRAME_F( 13 )
232#define RISCV_INTERRUPT_FRAME_FA2 RISCV_INTERRUPT_FRAME_F( 14 )
233#define RISCV_INTERRUPT_FRAME_FA3 RISCV_INTERRUPT_FRAME_F( 15 )
234#define RISCV_INTERRUPT_FRAME_FA4 RISCV_INTERRUPT_FRAME_F( 16 )
235#define RISCV_INTERRUPT_FRAME_FA5 RISCV_INTERRUPT_FRAME_F( 17 )
236#define RISCV_INTERRUPT_FRAME_FA6 RISCV_INTERRUPT_FRAME_F( 18 )
237#define RISCV_INTERRUPT_FRAME_FA7 RISCV_INTERRUPT_FRAME_F( 19 )
238
239#endif /* __riscv_flen */
240
241#ifndef ASM
242
243#ifdef __cplusplus
244extern "C" {
245#endif
246
247typedef struct {
248  uintptr_t mstatus;
249  uintptr_t mepc;
250  uintptr_t a2;
251  uintptr_t s0;
252  uintptr_t s1;
253  uintptr_t ra;
254  uintptr_t a3;
255  uintptr_t a4;
256  uintptr_t a5;
257  uintptr_t a6;
258  uintptr_t a7;
259  uintptr_t t0;
260  uintptr_t t1;
261  uintptr_t t2;
262  uintptr_t t3;
263  uintptr_t t4;
264  uintptr_t t5;
265  uintptr_t t6;
266#if __riscv_flen > 0
267  uint32_t fcsr;
268  RISCV_Float ft0;
269  RISCV_Float ft1;
270  RISCV_Float ft2;
271  RISCV_Float ft3;
272  RISCV_Float ft4;
273  RISCV_Float ft5;
274  RISCV_Float ft6;
275  RISCV_Float ft7;
276  RISCV_Float ft8;
277  RISCV_Float ft9;
278  RISCV_Float ft10;
279  RISCV_Float ft11;
280  RISCV_Float fa0;
281  RISCV_Float fa1;
282  RISCV_Float fa2;
283  RISCV_Float fa3;
284  RISCV_Float fa4;
285  RISCV_Float fa5;
286  RISCV_Float fa6;
287  RISCV_Float fa7;
288#endif
289  uintptr_t a0;
290  uintptr_t a1;
291} RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame;
292
293#ifdef __riscv_atomic
294typedef struct {
295  uint64_t clear_reservations;
296  uint32_t reserved_for_alignment_of_interrupt_frame[ 2 ];
297} CPU_Per_CPU_control;
298#endif
299
300static inline uint32_t _RISCV_Read_FCSR( void )
301{
302  uint32_t fcsr;
303
304  __asm__ volatile ( "frcsr %0" : "=&r" ( fcsr ) );
305
306  return fcsr;
307}
308
309#ifdef RTEMS_SMP
310
311static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void )
312{
313  struct Per_CPU_Control *cpu_self;
314
315  __asm__ volatile ( "csrr %0, mscratch" : "=r" ( cpu_self ) );
316
317  return cpu_self;
318}
319
320#define _CPU_Get_current_per_CPU_control() _RISCV_Get_current_per_CPU_control()
321
322#endif /* RTEMS_SMP */
323
324void _CPU_Context_volatile_clobber( uintptr_t pattern );
325
326void _CPU_Context_validate( uintptr_t pattern );
327
328RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
329{
330  __asm__ volatile ( "nop" );
331}
332
333#ifdef __cplusplus
334}
335#endif
336
337#endif /* ASM */
338
339#endif /* _RTEMS_SCORE_CPUIMPL_H */
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