source: rtems/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @ 5694b0c

Last change on this file since 5694b0c was 5694b0c, checked in by Sebastian Huber <sebastian.huber@…>, on Jul 19, 2018 at 8:15:53 AM

riscv: New CPU_Exception_frame

Use the CPU_Interrupt_frame for the volatile context. Add non-volatile
registers and extra state on top of it.

Update #3433.

  • Property mode set to 100644
File size: 10.2 KB
Line 
1/**
2 * @file
3 *
4 * @brief CPU Port Implementation API
5 */
6
7/*
8 * Copyright (c) 2013, 2018 embedded brains GmbH
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#ifndef _RTEMS_SCORE_CPUIMPL_H
33#define _RTEMS_SCORE_CPUIMPL_H
34
35#include <rtems/score/cpu.h>
36
37#ifdef __riscv_atomic
38#define CPU_PER_CPU_CONTROL_SIZE 16
39#else
40#define CPU_PER_CPU_CONTROL_SIZE 0
41#endif
42
43#ifdef RTEMS_SMP
44#define RISCV_CONTEXT_IS_EXECUTING 0
45#endif
46
47#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 4
48
49#if __riscv_xlen == 32
50
51#define RISCV_CONTEXT_RA 8
52#define RISCV_CONTEXT_SP 12
53#define RISCV_CONTEXT_TP 16
54#define RISCV_CONTEXT_S0 20
55#define RISCV_CONTEXT_S1 24
56#define RISCV_CONTEXT_S2 28
57#define RISCV_CONTEXT_S3 32
58#define RISCV_CONTEXT_S4 36
59#define RISCV_CONTEXT_S5 40
60#define RISCV_CONTEXT_S6 44
61#define RISCV_CONTEXT_S7 48
62#define RISCV_CONTEXT_S8 52
63#define RISCV_CONTEXT_S9 56
64#define RISCV_CONTEXT_S10 60
65#define RISCV_CONTEXT_S11 64
66
67#define RISCV_INTERRUPT_FRAME_MSTATUS 0
68#define RISCV_INTERRUPT_FRAME_MEPC 4
69#define RISCV_INTERRUPT_FRAME_A2 8
70#define RISCV_INTERRUPT_FRAME_S0 12
71#define RISCV_INTERRUPT_FRAME_S1 16
72#define RISCV_INTERRUPT_FRAME_RA 20
73#define RISCV_INTERRUPT_FRAME_A3 24
74#define RISCV_INTERRUPT_FRAME_A4 28
75#define RISCV_INTERRUPT_FRAME_A5 32
76#define RISCV_INTERRUPT_FRAME_A6 36
77#define RISCV_INTERRUPT_FRAME_A7 40
78#define RISCV_INTERRUPT_FRAME_T0 44
79#define RISCV_INTERRUPT_FRAME_T1 48
80#define RISCV_INTERRUPT_FRAME_T2 52
81#define RISCV_INTERRUPT_FRAME_T3 56
82#define RISCV_INTERRUPT_FRAME_T4 60
83#define RISCV_INTERRUPT_FRAME_T5 64
84#define RISCV_INTERRUPT_FRAME_T6 68
85
86#if __riscv_flen == 0
87
88#define RISCV_INTERRUPT_FRAME_A0 72
89#define RISCV_INTERRUPT_FRAME_A1 76
90
91#define CPU_INTERRUPT_FRAME_SIZE 80
92
93#elif __riscv_flen == 32
94
95#define RISCV_CONTEXT_FCSR 68
96
97#define RISCV_CONTEXT_F( x ) ( 72 + 4 * x )
98
99#define RISCV_INTERRUPT_FRAME_FCSR 72
100
101#define RISCV_INTERRUPT_FRAME_F( x ) ( 76 + 4 * x )
102
103#define RISCV_INTERRUPT_FRAME_A0 156
104#define RISCV_INTERRUPT_FRAME_A1 160
105
106#define CPU_INTERRUPT_FRAME_SIZE 176
107
108#elif __riscv_flen == 64
109
110#define RISCV_CONTEXT_FCSR 68
111
112#define RISCV_CONTEXT_F( x ) ( 72 + 8 * x )
113
114#define RISCV_INTERRUPT_FRAME_FCSR 72
115
116#define RISCV_INTERRUPT_FRAME_F( x ) ( 80 + 8 * x )
117
118#define RISCV_INTERRUPT_FRAME_A0 240
119#define RISCV_INTERRUPT_FRAME_A1 244
120
121#define CPU_INTERRUPT_FRAME_SIZE 256
122
123#endif /* __riscv_flen */
124
125#define RISCV_EXCEPTION_FRAME_X( x ) ( CPU_INTERRUPT_FRAME_SIZE + 4 * x )
126
127#elif __riscv_xlen == 64
128
129#define RISCV_CONTEXT_RA 8
130#define RISCV_CONTEXT_SP 16
131#define RISCV_CONTEXT_TP 24
132#define RISCV_CONTEXT_S0 32
133#define RISCV_CONTEXT_S1 40
134#define RISCV_CONTEXT_S2 48
135#define RISCV_CONTEXT_S3 56
136#define RISCV_CONTEXT_S4 64
137#define RISCV_CONTEXT_S5 72
138#define RISCV_CONTEXT_S6 80
139#define RISCV_CONTEXT_S7 88
140#define RISCV_CONTEXT_S8 96
141#define RISCV_CONTEXT_S9 104
142#define RISCV_CONTEXT_S10 112
143#define RISCV_CONTEXT_S11 120
144
145#define RISCV_INTERRUPT_FRAME_MSTATUS 0
146#define RISCV_INTERRUPT_FRAME_MEPC 8
147#define RISCV_INTERRUPT_FRAME_A2 16
148#define RISCV_INTERRUPT_FRAME_S0 24
149#define RISCV_INTERRUPT_FRAME_S1 32
150#define RISCV_INTERRUPT_FRAME_RA 40
151#define RISCV_INTERRUPT_FRAME_A3 48
152#define RISCV_INTERRUPT_FRAME_A4 56
153#define RISCV_INTERRUPT_FRAME_A5 64
154#define RISCV_INTERRUPT_FRAME_A6 72
155#define RISCV_INTERRUPT_FRAME_A7 80
156#define RISCV_INTERRUPT_FRAME_T0 88
157#define RISCV_INTERRUPT_FRAME_T1 96
158#define RISCV_INTERRUPT_FRAME_T2 104
159#define RISCV_INTERRUPT_FRAME_T3 112
160#define RISCV_INTERRUPT_FRAME_T4 120
161#define RISCV_INTERRUPT_FRAME_T5 128
162#define RISCV_INTERRUPT_FRAME_T6 136
163
164#if __riscv_flen == 0
165
166#define RISCV_INTERRUPT_FRAME_A0 144
167#define RISCV_INTERRUPT_FRAME_A1 152
168
169#define CPU_INTERRUPT_FRAME_SIZE 160
170
171#elif __riscv_flen == 32
172
173#define RISCV_CONTEXT_FCSR 128
174
175#define RISCV_CONTEXT_F( x ) ( 132 + 4 * x )
176
177#define RISCV_INTERRUPT_FRAME_FCSR 144
178
179#define RISCV_INTERRUPT_FRAME_F( x ) ( 148 + 4 * x )
180
181#define RISCV_INTERRUPT_FRAME_A0 232
182#define RISCV_INTERRUPT_FRAME_A1 240
183
184#define CPU_INTERRUPT_FRAME_SIZE 256
185
186#elif __riscv_flen == 64
187
188#define RISCV_CONTEXT_FCSR 128
189
190#define RISCV_CONTEXT_F( x ) ( 136 + 8 * x )
191
192#define RISCV_INTERRUPT_FRAME_FCSR 144
193
194#define RISCV_INTERRUPT_FRAME_F( x ) ( 152 + 8 * x )
195
196#define RISCV_INTERRUPT_FRAME_A0 312
197#define RISCV_INTERRUPT_FRAME_A1 320
198
199#define CPU_INTERRUPT_FRAME_SIZE 336
200
201#endif /* __riscv_flen */
202
203#define RISCV_EXCEPTION_FRAME_X( x ) ( CPU_INTERRUPT_FRAME_SIZE + 8 * x )
204
205#endif /* __riscv_xlen */
206
207#define RISCV_EXCEPTION_FRAME_MCAUSE RISCV_EXCEPTION_FRAME_X( 0 )
208#define RISCV_EXCEPTION_FRAME_SP RISCV_EXCEPTION_FRAME_X( 1 )
209#define RISCV_EXCEPTION_FRAME_GP RISCV_EXCEPTION_FRAME_X( 2 )
210#define RISCV_EXCEPTION_FRAME_TP RISCV_EXCEPTION_FRAME_X( 3 )
211#define RISCV_EXCEPTION_FRAME_S2 RISCV_EXCEPTION_FRAME_X( 4 )
212#define RISCV_EXCEPTION_FRAME_S3 RISCV_EXCEPTION_FRAME_X( 5 )
213#define RISCV_EXCEPTION_FRAME_S4 RISCV_EXCEPTION_FRAME_X( 6 )
214#define RISCV_EXCEPTION_FRAME_S5 RISCV_EXCEPTION_FRAME_X( 7 )
215#define RISCV_EXCEPTION_FRAME_S6 RISCV_EXCEPTION_FRAME_X( 8 )
216#define RISCV_EXCEPTION_FRAME_S7 RISCV_EXCEPTION_FRAME_X( 9 )
217#define RISCV_EXCEPTION_FRAME_S8 RISCV_EXCEPTION_FRAME_X( 10 )
218#define RISCV_EXCEPTION_FRAME_S9 RISCV_EXCEPTION_FRAME_X( 11 )
219#define RISCV_EXCEPTION_FRAME_S10 RISCV_EXCEPTION_FRAME_X( 12 )
220#define RISCV_EXCEPTION_FRAME_S11 RISCV_EXCEPTION_FRAME_X( 13 )
221
222#if __riscv_flen > 0
223
224#define RISCV_CONTEXT_FS0 RISCV_CONTEXT_F( 0 )
225#define RISCV_CONTEXT_FS1 RISCV_CONTEXT_F( 1 )
226#define RISCV_CONTEXT_FS2 RISCV_CONTEXT_F( 2 )
227#define RISCV_CONTEXT_FS3 RISCV_CONTEXT_F( 3 )
228#define RISCV_CONTEXT_FS4 RISCV_CONTEXT_F( 4 )
229#define RISCV_CONTEXT_FS5 RISCV_CONTEXT_F( 5 )
230#define RISCV_CONTEXT_FS6 RISCV_CONTEXT_F( 6 )
231#define RISCV_CONTEXT_FS7 RISCV_CONTEXT_F( 7 )
232#define RISCV_CONTEXT_FS8 RISCV_CONTEXT_F( 8 )
233#define RISCV_CONTEXT_FS9 RISCV_CONTEXT_F( 9 )
234#define RISCV_CONTEXT_FS10 RISCV_CONTEXT_F( 10 )
235#define RISCV_CONTEXT_FS11 RISCV_CONTEXT_F( 11 )
236
237#define RISCV_INTERRUPT_FRAME_FT0 RISCV_INTERRUPT_FRAME_F( 0 )
238#define RISCV_INTERRUPT_FRAME_FT1 RISCV_INTERRUPT_FRAME_F( 1 )
239#define RISCV_INTERRUPT_FRAME_FT2 RISCV_INTERRUPT_FRAME_F( 2 )
240#define RISCV_INTERRUPT_FRAME_FT3 RISCV_INTERRUPT_FRAME_F( 3 )
241#define RISCV_INTERRUPT_FRAME_FT4 RISCV_INTERRUPT_FRAME_F( 4 )
242#define RISCV_INTERRUPT_FRAME_FT5 RISCV_INTERRUPT_FRAME_F( 5 )
243#define RISCV_INTERRUPT_FRAME_FT6 RISCV_INTERRUPT_FRAME_F( 6 )
244#define RISCV_INTERRUPT_FRAME_FT7 RISCV_INTERRUPT_FRAME_F( 7 )
245#define RISCV_INTERRUPT_FRAME_FT8 RISCV_INTERRUPT_FRAME_F( 8 )
246#define RISCV_INTERRUPT_FRAME_FT9 RISCV_INTERRUPT_FRAME_F( 9 )
247#define RISCV_INTERRUPT_FRAME_FT10 RISCV_INTERRUPT_FRAME_F( 10 )
248#define RISCV_INTERRUPT_FRAME_FT11 RISCV_INTERRUPT_FRAME_F( 11 )
249#define RISCV_INTERRUPT_FRAME_FA0 RISCV_INTERRUPT_FRAME_F( 12 )
250#define RISCV_INTERRUPT_FRAME_FA1 RISCV_INTERRUPT_FRAME_F( 13 )
251#define RISCV_INTERRUPT_FRAME_FA2 RISCV_INTERRUPT_FRAME_F( 14 )
252#define RISCV_INTERRUPT_FRAME_FA3 RISCV_INTERRUPT_FRAME_F( 15 )
253#define RISCV_INTERRUPT_FRAME_FA4 RISCV_INTERRUPT_FRAME_F( 16 )
254#define RISCV_INTERRUPT_FRAME_FA5 RISCV_INTERRUPT_FRAME_F( 17 )
255#define RISCV_INTERRUPT_FRAME_FA6 RISCV_INTERRUPT_FRAME_F( 18 )
256#define RISCV_INTERRUPT_FRAME_FA7 RISCV_INTERRUPT_FRAME_F( 19 )
257
258#if __riscv_flen == 32
259#define RISCV_EXCEPTION_FRAME_F( x ) ( RISCV_EXCEPTION_FRAME_X( 14 ) + 4 * x )
260#elif __riscv_flen == 64
261#define RISCV_EXCEPTION_FRAME_F( x ) ( RISCV_EXCEPTION_FRAME_X( 14 ) + 8 * x )
262#endif
263
264#define RISCV_EXCEPTION_FRAME_FS0 RISCV_EXCEPTION_FRAME_F( 0 )
265#define RISCV_EXCEPTION_FRAME_FS1 RISCV_EXCEPTION_FRAME_F( 1 )
266#define RISCV_EXCEPTION_FRAME_FS2 RISCV_EXCEPTION_FRAME_F( 2 )
267#define RISCV_EXCEPTION_FRAME_FS3 RISCV_EXCEPTION_FRAME_F( 3 )
268#define RISCV_EXCEPTION_FRAME_FS4 RISCV_EXCEPTION_FRAME_F( 4 )
269#define RISCV_EXCEPTION_FRAME_FS5 RISCV_EXCEPTION_FRAME_F( 5 )
270#define RISCV_EXCEPTION_FRAME_FS6 RISCV_EXCEPTION_FRAME_F( 6 )
271#define RISCV_EXCEPTION_FRAME_FS7 RISCV_EXCEPTION_FRAME_F( 7 )
272#define RISCV_EXCEPTION_FRAME_FS8 RISCV_EXCEPTION_FRAME_F( 8 )
273#define RISCV_EXCEPTION_FRAME_FS9 RISCV_EXCEPTION_FRAME_F( 9 )
274#define RISCV_EXCEPTION_FRAME_FS10 RISCV_EXCEPTION_FRAME_F( 10 )
275#define RISCV_EXCEPTION_FRAME_FS11 RISCV_EXCEPTION_FRAME_F( 11 )
276
277#endif /* __riscv_flen */
278
279#ifndef ASM
280
281#ifdef __cplusplus
282extern "C" {
283#endif
284
285#ifdef __riscv_atomic
286typedef struct {
287  uint64_t clear_reservations;
288  uint32_t reserved_for_alignment_of_interrupt_frame[ 2 ];
289} CPU_Per_CPU_control;
290#endif
291
292static inline uint32_t _RISCV_Read_FCSR( void )
293{
294  uint32_t fcsr;
295
296  __asm__ volatile ( "frcsr %0" : "=&r" ( fcsr ) );
297
298  return fcsr;
299}
300
301#ifdef RTEMS_SMP
302
303static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void )
304{
305  struct Per_CPU_Control *cpu_self;
306
307  __asm__ volatile ( "csrr %0, mscratch" : "=r" ( cpu_self ) );
308
309  return cpu_self;
310}
311
312#define _CPU_Get_current_per_CPU_control() _RISCV_Get_current_per_CPU_control()
313
314#endif /* RTEMS_SMP */
315
316void _CPU_Context_volatile_clobber( uintptr_t pattern );
317
318void _CPU_Context_validate( uintptr_t pattern );
319
320RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
321{
322  __asm__ volatile ( "unimp" );
323}
324
325RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
326{
327  __asm__ volatile ( "nop" );
328}
329
330#ifdef __cplusplus
331}
332#endif
333
334#endif /* ASM */
335
336#endif /* _RTEMS_SCORE_CPUIMPL_H */
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